From 7a042229036c3dde2b443788389d6adfe1c1dd67 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 29 Sep 2020 13:32:06 +0200 Subject: [PATCH] cpu/qemu-x86/cache_as_ram_bootblock: Fix wrong instruction The shld instruction does an arithmetic shift left on 64bit operants, but it's not the instruction we want, because what it actually does is shifting by cl, and storing the result in address 32. This wasn't noticed with QEMU as the DRAM is up and address 32 is valid. On real hardware when CAR is running this instruction causes a crash. Replace the instruction with the correct 64bit arithmetic left shift. Change-Id: Iedad9f4b693b1ea05898456eac2050a9389f6f19 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/45820 Reviewed-by: Christian Walter Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/qemu-x86/cache_as_ram_bootblock.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 148948ba31..197e0fd8e8 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -33,7 +33,7 @@ cache_as_ram: /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) movd %mm2, %rdi - shld %rdi, 32 + shlq $32, %rdi movd %mm1, %rsi or %rsi, %rdi