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mb/google/dedede: Enable SaGv support 

Allow MRC training in SaGv low, mid and high frequencies.

TEST=Verify memory trains at low, mid and high SaGv point
     through FSP debug logs enabled.

Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2020-09-09 14:34:36 +05:30 committed by Patrick Georgi
parent e9984c8e4f
commit 7a04d05f1d
1 changed files with 3 additions and 0 deletions
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src/mainboard/google/dedede/variants/baseboard/devicetree.cb
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@ -168,6 +168,9 @@ chip soc/intel/jasperlake
# Skip the CPU repalcement check # Skip the CPU repalcement check
register "SkipCpuReplacementCheck" = "1" register "SkipCpuReplacementCheck" = "1"
# Sagv Configuration
register "SaGv" = "SaGv_Enabled"
# Set the minimum assertion width # Set the minimum assertion width
register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpS4MinAssert" = "1" # 1s