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southbridge/intel: add IS_ENABLED() around Kconfig symbol references 

Change-Id: I2b532522938123bb7844cef94cda0b44bcb98e45
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth 2017-06-24 21:29:38 -06:00
parent 9fa8ebe1a4
commit 7a1a3ad2ce
48 changed files with 119 additions and 119 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/intel/bd82x6x/finalize.c
View File

@ -45,7 +45,7 @@ void intel_pch_finalize_smm(void)
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
#if CONFIG_SPI_FLASH_SMM
#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif

6
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -76,7 +76,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@ -285,7 +285,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
@ -668,7 +668,7 @@ static void southbridge_inject_dsdt(device_t dev)
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
chromeos_init_vboot(&(gnvs->chromeos));
#endif

10
src/southbridge/intel/bd82x6x/me.c
View File

@ -42,7 +42,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -61,7 +61,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -457,7 +457,7 @@ static int mkhi_get_fwcaps(void)
}
#endif
#if CONFIG_CHROMEOS && 0 /* DISABLED */
#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
int mkhi_global_reset(void)
{
@ -589,7 +589,7 @@ static me_bios_path intel_me_path(device_t dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -678,7 +678,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif

12
src/southbridge/intel/bd82x6x/me_8.x.c
View File

@ -42,7 +42,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -63,7 +63,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -424,7 +424,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
}
#endif
#if CONFIG_CHROMEOS && 0 /* DISABLED */
#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@ -576,7 +576,7 @@ static me_bios_path intel_me_path(device_t dev)
path = ME_ERROR_BIOS_PATH;
}
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -665,7 +665,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@ -706,7 +706,7 @@ static void intel_me_init(device_t dev)
if (intel_me_read_mbp(&mbp_data))
break;
#if CONFIG_CHROMEOS && 0 /* DISABLED */
#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/*
* Unlock ME in recovery mode.
*/

2
src/southbridge/intel/bd82x6x/pch.h
View File

@ -75,7 +75,7 @@ int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else /* __PRE_RAM__ */

2
src/southbridge/intel/bd82x6x/smi.c
View File

@ -227,7 +227,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif

8
src/southbridge/intel/bd82x6x/smihandler.c
View File

@ -432,7 +432,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@ -534,7 +534,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@ -621,7 +621,7 @@ static void southbridge_smi_apmc(void)
mainboard_finalized = 1;
break;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@ -645,7 +645,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);

2
src/southbridge/intel/common/spi.c
View File

@ -188,7 +188,7 @@ enum {
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
};
#if CONFIG_DEBUG_SPI_FLASH
#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
static u8 readb_(const void *addr)
{

4
src/southbridge/intel/common/usb_debug.c
View File

@ -27,7 +27,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
u32 class;
pci_devfn_t dev;
#if CONFIG_HAVE_USBDEBUG_OPTIONS
#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
if (hcd_idx==2)
dev = PCI_DEV(0, 0x1a, 0);
else
@ -37,7 +37,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
#endif
class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
#if CONFIG_HAVE_USBDEBUG_OPTIONS
#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)
if (class != PCI_EHCI_CLASSCODE) {
/* If we enter here before RCBA programming, EHCI function may
* appear with the highest function number instead.

4
src/southbridge/intel/fsp_bd82x6x/early_init.c
View File

@ -151,7 +151,7 @@ static void sandybridge_setup_bars(void)
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@ -160,7 +160,7 @@ static void sandybridge_setup_bars(void)
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)

2
src/southbridge/intel/fsp_bd82x6x/finalize.c
View File

@ -30,7 +30,7 @@ void intel_pch_finalize_smm(void)
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
#if CONFIG_SPI_FLASH_SMM
#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif

4
src/southbridge/intel/fsp_bd82x6x/lpc.c
View File

@ -85,7 +85,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@ -295,7 +295,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}

10
src/southbridge/intel/fsp_bd82x6x/me.c
View File

@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -456,7 +456,7 @@ static int mkhi_get_fwcaps(void)
}
#endif
#if CONFIG_CHROMEOS && 0 /* DISABLED */
#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
int mkhi_global_reset(void)
{
@ -588,7 +588,7 @@ static me_bios_path intel_me_path(device_t dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -677,7 +677,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif

12
src/southbridge/intel/fsp_bd82x6x/me_8.x.c
View File

@ -40,7 +40,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -422,7 +422,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
}
#endif
#if CONFIG_CHROMEOS && 0 /* DISABLED */
#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@ -574,7 +574,7 @@ static me_bios_path intel_me_path(device_t dev)
path = ME_ERROR_BIOS_PATH;
}
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -663,7 +663,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@ -704,7 +704,7 @@ static void intel_me_init(device_t dev)
if (intel_me_read_mbp(&mbp_data))
break;
#if CONFIG_CHROMEOS && 0 /* DISABLED */
#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/*
* Unlock ME in recovery mode.
*/

2
src/southbridge/intel/fsp_bd82x6x/pch.h
View File

@ -67,7 +67,7 @@ int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_enable(device_t dev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else

2
src/southbridge/intel/fsp_bd82x6x/smi.c
View File

@ -227,7 +227,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif

8
src/southbridge/intel/fsp_bd82x6x/smihandler.c
View File

@ -331,7 +331,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@ -433,7 +433,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@ -505,7 +505,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@ -529,7 +529,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);

4
src/southbridge/intel/fsp_i89xx/early_init.c
View File

@ -38,7 +38,7 @@ static void sandybridge_setup_bars(void)
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter for non-S3 resume */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)
@ -47,7 +47,7 @@ static void sandybridge_setup_bars(void)
printk(BIOS_DEBUG, " done.\n");
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
/* Increment Boot Counter except when resuming from S3 */
if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)

2
src/southbridge/intel/fsp_i89xx/finalize.c
View File

@ -30,7 +30,7 @@ void intel_pch_finalize_smm(void)
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
#if CONFIG_SPI_FLASH_SMM
#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif

4
src/southbridge/intel/fsp_i89xx/lpc.c
View File

@ -85,7 +85,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@ -295,7 +295,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}

8
src/southbridge/intel/fsp_i89xx/me.c
View File

@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -555,7 +555,7 @@ static me_bios_path intel_me_path(device_t dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -644,7 +644,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif

8
src/southbridge/intel/fsp_i89xx/me_8.x.c
View File

@ -40,7 +40,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data);
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -543,7 +543,7 @@ static me_bios_path intel_me_path(device_t dev)
path = ME_ERROR_BIOS_PATH;
}
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -632,7 +632,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif

2
src/southbridge/intel/fsp_i89xx/pch.h
View File

@ -65,7 +65,7 @@ int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_enable(device_t dev);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else

2
src/southbridge/intel/fsp_i89xx/romstage.c
View File

@ -137,7 +137,7 @@ void main(FSP_INFO_HEADER *fsp_info_header)
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
post_code(0x46);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but

2
src/southbridge/intel/fsp_i89xx/smi.c
View File

@ -227,7 +227,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif

8
src/southbridge/intel/fsp_i89xx/smihandler.c
View File

@ -331,7 +331,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@ -433,7 +433,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@ -505,7 +505,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@ -529,7 +529,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);

4
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -94,7 +94,7 @@ static void soc_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
write8(ibase + ILB_SERIRQ_CNTL, (1 << 7));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
write8(ibase + ILB_SERIRQ_CNTL, 0);
#endif
}
@ -435,7 +435,7 @@ static void southbridge_inject_dsdt(device_t dev)
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
acpi_save_gnvs((unsigned long)gnvs);
#if CONFIG_HAVE_SMI_HANDLER
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
#endif

2
src/southbridge/intel/fsp_rangeley/soc.h
View File

@ -65,7 +65,7 @@ void soc_enable(device_t dev);
#include <arch/acpi.h>
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
void soc_log_state(void);
#endif
#else

6
src/southbridge/intel/i82371eb/isa.c
View File

@ -28,7 +28,7 @@
#endif
#include "i82371eb.h"
#if CONFIG_IOAPIC
#if IS_ENABLED(CONFIG_IOAPIC)
static void enable_intel_82093aa_ioapic(void)
{
u16 reg16;
@ -84,7 +84,7 @@ static void isa_init(struct device *dev)
/* Initialize ISA DMA. */
isa_dma_init();
#if CONFIG_IOAPIC
#if IS_ENABLED(CONFIG_IOAPIC)
/*
* Unlike most other southbridges the 82371EB doesn't have a built-in
* IOAPIC. Instead, 82371EB-based boards that support multiple CPUs
@ -115,7 +115,7 @@ static void sb_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED |
IORESOURCE_RESERVE;
#if CONFIG_IOAPIC
#if IS_ENABLED(CONFIG_IOAPIC)
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;

4
src/southbridge/intel/i82801gx/lpc.c
View File

@ -329,7 +329,7 @@ static void enable_clock_gating(void)
RCBA32(CG) = reg32;
}
#if CONFIG_HAVE_SMI_HANDLER
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
static void i82801gx_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@ -448,7 +448,7 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
#if CONFIG_HAVE_SMI_HANDLER
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
i82801gx_lock_smm(dev);
#endif

2
src/southbridge/intel/i82801gx/smihandler.c
View File

@ -414,7 +414,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
}
#if !CONFIG_SMM_TSEG
#if !IS_ENABLED(CONFIG_SMM_TSEG)
/* Unlock the SMI semaphore. We're currently in SMM, and the semaphore
* will never be unlocked because the next outl will switch off the CPU.
* This might open a small race between the smi_release_lock() and the outl()

2
src/southbridge/intel/i82801ix/acpi/sleepstates.asl
View File

@ -15,7 +15,7 @@
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
#if !CONFIG_HAVE_ACPI_RESUME
#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
Name(\_S1, Package(){0x1,0x0,0x0,0x0})
#else
Name(\_S3, Package(){0x5,0x0,0x0,0x0})

2
src/southbridge/intel/i82801ix/i82801ix.c
View File

@ -222,7 +222,7 @@ static void i82801ix_init(void *chip_info)
i82801ix_hide_functions();
/* Reset watchdog timer. */
#if !CONFIG_HAVE_SMI_HANDLER
#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */
#endif
outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */

4
src/southbridge/intel/i82801ix/lpc.c
View File

@ -369,7 +369,7 @@ static void enable_clock_gating(void)
RCBA32(0x38c0) |= 7;
}
#if CONFIG_HAVE_SMI_HANDLER
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
static void i82801ix_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
@ -464,7 +464,7 @@ static void lpc_init(struct device *dev)
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
#if CONFIG_HAVE_SMI_HANDLER
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
i82801ix_lock_smm(dev);
#endif
}

4
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -71,7 +71,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@ -280,7 +280,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}

8
src/southbridge/intel/ibexpeak/me.c
View File

@ -41,7 +41,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -470,7 +470,7 @@ static me_bios_path intel_me_path(device_t dev)
if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -559,7 +559,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif

2
src/southbridge/intel/ibexpeak/pch.h
View File

@ -70,7 +70,7 @@ int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void gpi_route_interrupt(u8 gpi, u8 mode);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
#else /* __PRE_RAM__ */

2
src/southbridge/intel/ibexpeak/smi.c
View File

@ -228,7 +228,7 @@ void southbridge_smm_init(void)
u16 pm1_en;
u32 gpe0_en;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif

8
src/southbridge/intel/ibexpeak/smihandler.c
View File

@ -433,7 +433,7 @@ static void southbridge_smi_sleep(void)
/* Do any mainboard sleep handling */
mainboard_smi_sleep(slp_typ);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@ -535,7 +535,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@ -607,7 +607,7 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@ -631,7 +631,7 @@ static void southbridge_smi_pm1(void)
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
outl(reg32, pmbase + PM1_CNT);

2
src/southbridge/intel/lynxpoint/acpi/pch.asl
View File

@ -96,7 +96,7 @@ Scope(\)
#include "smbus.asl"
// Serial IO
#if CONFIG_INTEL_LYNXPOINT_LP
#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#include "serialio.asl"
#include "lpt_lp.asl"
#endif

6
src/southbridge/intel/lynxpoint/early_pch.c
View File

@ -24,7 +24,7 @@
#include "pch.h"
#include "chip.h"
#if CONFIG_INTEL_LYNXPOINT_LP
#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
#else
#include "southbridge/intel/common/gpio.h"
@ -133,7 +133,7 @@ int early_pch_init(const void *gpio_map,
pch_enable_bars();
#if CONFIG_INTEL_LYNXPOINT_LP
#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
setup_pch_lp_gpios(gpio_map);
#else
setup_pch_gpios(gpio_map);
@ -154,7 +154,7 @@ int early_pch_init(const void *gpio_map,
wake_from_s3 = sleep_type_s3();
#if CONFIG_ELOG_BOOT_COUNT
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
if (!wake_from_s3)
boot_count_increment();
#endif

2
src/southbridge/intel/lynxpoint/finalize.c
View File

@ -34,7 +34,7 @@ void intel_pch_finalize_smm(void)
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
#if CONFIG_SPI_FLASH_SMM
#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif

8
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -77,7 +77,7 @@ static void pch_enable_serial_irqs(struct device *dev)
/* Set packet length and toggle silent mode bit for one frame. */
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
pci_write_config8(dev, SERIRQ_CNTL,
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
#endif
@ -292,7 +292,7 @@ static void pch_rtc_init(struct device *dev)
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
elog_add_event(ELOG_TYPE_RTC_RESET);
#endif
}
@ -498,7 +498,7 @@ static void enable_lp_clock_gating(device_t dev)
static void pch_set_acpi_mode(void)
{
#if CONFIG_HAVE_SMI_HANDLER
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
@ -760,7 +760,7 @@ static void southbridge_inject_dsdt(device_t dev)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
chromeos_init_vboot(&(gnvs->chromeos));
#endif

18
src/southbridge/intel/lynxpoint/me_9.x.c
View File

@ -37,7 +37,7 @@
#include "me.h"
#include "pch.h"
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@ -59,7 +59,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
static u32 *mei_base_address;
void intel_me_mbp_clear(device_t dev);
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
{
struct mei_csr *csr;
@ -519,7 +519,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap)
#endif /* CONFIG_DEBUG_INTEL_ME */
#endif
#if CONFIG_CHROMEOS && 0 /* DISABLED */
#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */
/* Tell ME to issue a global reset */
static int mkhi_global_reset(void)
{
@ -579,7 +579,7 @@ void intel_me_finalize_smm(void)
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
#if CONFIG_ME_MBP_CLEAR_LATE
#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)
/* Wait for ME MBP Cleared indicator */
intel_me_mbp_clear(PCH_ME_DEV);
#endif
@ -707,7 +707,7 @@ static me_bios_path intel_me_path(device_t dev)
path = ME_ERROR_BIOS_PATH;
}
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
if (path != ME_NORMAL_BIOS_PATH) {
struct elog_event_data_me_extended data = {
.current_working_state = hfs.working_state,
@ -796,7 +796,7 @@ static int intel_me_extend_valid(device_t dev)
}
printk(BIOS_DEBUG, "\n");
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count);
#endif
@ -835,7 +835,7 @@ static void intel_me_init(device_t dev)
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
me_print_fw_version(mbp_data.fw_version_name);
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
me_print_fwcaps(mbp_data.fw_capabilities);
#endif
@ -991,7 +991,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
host.interrupt_generate = 1;
write_host_csr(&host);
#if !CONFIG_ME_MBP_CLEAR_LATE
#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE)
/* Wait for the mbp_cleared indicator. */
intel_me_mbp_clear(dev);
#endif
@ -1000,7 +1000,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
mbp->header.num_entries, mbp->header.mbp_size);
#if CONFIG_DEBUG_INTEL_ME
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
for (i = 0; i < mbp->header.mbp_size - 1; i++) {
printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
}

4
src/southbridge/intel/lynxpoint/pch.h
View File

@ -72,7 +72,7 @@
#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
#if CONFIG_INTEL_LYNXPOINT_LP
#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#define DEFAULT_PMBASE 0x1000
#define DEFAULT_GPIOBASE 0x1400
#define DEFAULT_GPIOSIZE 0x400
@ -181,7 +181,7 @@ void pch_disable_devfn(device_t dev);
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
void pch_log_state(void);
#endif
void acpi_create_intel_hpet(acpi_hpet_t * hpet);

2
src/southbridge/intel/lynxpoint/pmutil.c
View File

@ -26,7 +26,7 @@
#include <console/console.h>
#include "pch.h"
#if CONFIG_INTEL_LYNXPOINT_LP
#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
#include "lp_gpio.h"
#endif

4
src/southbridge/intel/lynxpoint/smi.c
View File

@ -29,7 +29,7 @@ void southbridge_smm_clear_state(void)
{
u32 smi_en;
#if CONFIG_ELOG
#if IS_ENABLED(CONFIG_ELOG)
/* Log events from chipset before clearing */
pch_log_state();
#endif
@ -123,7 +123,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
/*
* Finalize system before payload boot if not in ChromeOS environment.
*/
#if !CONFIG_CHROMEOS
#if !IS_ENABLED(CONFIG_CHROMEOS)
static void finalize_boot(void *unused)
{

10
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -130,13 +130,13 @@ static void southbridge_smi_sleep(void)
mainboard_smi_sleep(slp_typ);
/* USB sleep preparations */
#if !CONFIG_FINALIZE_USB_ROUTE_XHCI
#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI)
usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ);
usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ);
#endif
usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ);
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log S3, S4, and S5 entry */
if (slp_typ >= ACPI_S3)
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
@ -243,7 +243,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
return NULL;
}
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
@ -314,7 +314,7 @@ static void southbridge_smi_apmc(void)
case 0xca:
usb_xhci_route_all();
break;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
case ELOG_GSMI_APM_CNT:
southbridge_smi_gsmi();
break;
@ -333,7 +333,7 @@ static void southbridge_smi_pm1(void)
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
disable_pm1_control(-1UL);