diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index f5ed8927c9..b43987d13c 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -111,6 +111,9 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
  */
 uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
 
+/* Get PCH root port groups */
+const struct pcie_rp_group *soc_get_pch_rp_groups(void);
+
 enum pcie_rp_type {
 	PCIE_RP_UNKNOWN,
 	PCIE_RP_CPU,
diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c
index 5966af6c2b..f45a9c4e96 100644
--- a/src/soc/intel/tigerlake/pcie_rp.c
+++ b/src/soc/intel/tigerlake/pcie_rp.c
@@ -12,6 +12,13 @@ static const struct pcie_rp_group pch_lp_rp_groups[] = {
 	{ 0 }
 };
 
+static const struct pcie_rp_group pch_h_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8 },
+	{ 0 }
+};
+
 static const struct pcie_rp_group cpu_rp_groups[] = {
 	{ .slot = SA_DEV_SLOT_PEG,	.start = 0, .count = 3 },
 	{ .slot = SA_DEV_SLOT_CPU_PCIE,	.start = 0, .count = 1 },
@@ -40,9 +47,19 @@ static bool is_part_of_group(const struct device *dev,
 	return false;
 }
 
+const struct pcie_rp_group *soc_get_pch_rp_groups(void)
+{
+	if (CONFIG(SOC_INTEL_TIGERLAKE_PCH_H))
+		return pch_h_rp_groups;
+	else
+		return pch_lp_rp_groups;
+}
+
 enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev)
 {
-	if (is_part_of_group(dev, pch_lp_rp_groups))
+	const struct pcie_rp_group *pch_rp_groups = soc_get_pch_rp_groups();
+
+	if (is_part_of_group(dev, pch_rp_groups))
 		return PCIE_RP_PCH;
 
 	if (is_part_of_group(dev, cpu_rp_groups))