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intel/skylake: Implement HW Sequence based WP status read functionality 

Early(romstage) SPI write protected status read(wpsr) functionality
was broken causing 2 sec timeout issue.Implementing HW Seq based rd
status operation in romstage.

BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and tested using below command
flashrom -p host --wp-enable [this should enable WP on flash chip]
Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked)
flashrom -p host --wp-disable [this should disable WP on flash chip]
Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked)

Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488
Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294445
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Barnali Sarkar 2015-08-19 14:15:32 +05:30 committed by Patrick Georgi
parent d92f6127e1
commit 7a2defb2dd
1 changed files with 19 additions and 111 deletions
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130
src/soc/intel/skylake/romstage/spi.c
View File

@ -18,100 +18,21 @@
* Foundation, Inc. * Foundation, Inc.
*/ */
#include <arch/io.h> #include <flash_controller.h>
#include <console/console.h>
#include <delay.h>
#include <soc/spi.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#define SPI_DELAY 10 /* 10us */
#define SPI_RETRY 200000 /* 2s */
static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
{
u32 *ptr32 = (u32 *)buffer;
u32 i;
u16 hsfs, hsfc;
void *spibar = get_spi_bar();
/* Clear status bits */
hsfs = read16(spibar + SPIBAR_HSFS);
write16(spibar + SPIBAR_HSFS, hsfs | SPIBAR_HSFS_AEL |
SPIBAR_HSFS_FCERR | SPIBAR_HSFS_FDONE);
if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
printk(BIOS_ERR, "SPI ERROR: transaction in progress\n");
return -1;
}
/* Set flash address */
write32(spibar + SPIBAR_FADDR, offset);
/* Setup read transaction */
write16(spibar + SPIBAR_HSFC, SPIBAR_HSFC_BYTE_COUNT(size) |
SPIBAR_HSFC_CYCLE_READ);
/* Start transactinon */
hsfc = read16(spibar + SPIBAR_HSFC);
write16(spibar + SPIBAR_HSFC, hsfc | SPIBAR_HSFC_GO);
/* Wait for completion */
for (i = 0; i < SPI_RETRY; i++) {
if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
/* Cycle in progress, wait 1ms */
udelay(SPI_DELAY);
continue;
}
if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
printk(BIOS_ERR, "SPI ERROR: Access Error\n");
return -1;
}
if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n");
return -1;
}
break;
}
if (i >= SPI_RETRY) {
printk(BIOS_ERR, "SPI ERROR: Timeout\n");
return -1;
}
/* Read the data */
for (i = 0; i < size; i += sizeof(u32)) {
if (size-i >= 4) {
/* reading >= dword */
*ptr32++ = read32(spibar +
SPIBAR_FDATA(i/sizeof(u32)));
} else {
/* reading < dword */
u8 j, *ptr8 = (u8 *)ptr32;
u32 temp;
temp = read32(spibar +
SPIBAR_FDATA(i/sizeof(u32)));
for (j = 0; j < (size-i); j++) {
*ptr8++ = temp & 0xff;
temp >>= 8;
}
}
}
return size;
}
int early_spi_read(u32 offset, u32 size, u8 *buffer) int early_spi_read(u32 offset, u32 size, u8 *buffer)
{ {
u32 current = 0; u32 current = 0;
spi_init();
while (size > 0) { while (size > 0) {
u8 count = (size < 64) ? size : 64; u8 count = (size < 64) ? size : 64;
if (early_spi_read_block(offset + current, count, /* sending NULL for spiflash struct parameter since we are not
buffer + current) < 0) * calling HWSEQ read() call via Probe.
*/
if (pch_hwseq_read(NULL, offset + current, count,
buffer + current) != 0)
return -1; return -1;
size -= count; size -= count;
current += count; current += count;
@ -122,37 +43,24 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer)
/* /*
* Minimal set of commands to read WPSR from SPI. * Minimal set of commands to read WPSR from SPI.
* Don't use this code outside romstage -- it trashes the opmenu table.
* Returns 0 on success, < 0 on failure. * Returns 0 on success, < 0 on failure.
*/ */
int early_spi_read_wpsr(u8 *sr) int early_spi_read_wpsr(u8 *sr)
{ {
int retry; uint8_t rdsr;
void *spibar = get_spi_bar(); int ret = 0;
/* No address associated with rdsr */ spi_init();
write8(spibar + SPIBAR_OPTYPE, 0x0);
/* Setup opcode[0] = read wpsr */
write8(spibar + SPIBAR_OPMENU_LOWER, 0x5);
/* Start transaction */ /* sending NULL for spiflash struct parameter since we are not
write16(spibar + SPIBAR_SSFC, SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO); * calling HWSEQ read_status() call via Probe.
/* Wait for error / complete status */
for (retry = SPI_RETRY; retry; retry--) {
u16 status = read16(spibar + SPIBAR_SSFS);
if (status & SPIBAR_SSFS_ERROR) {
printk(BIOS_ERR, "SPI rdsr failed\n");
return -1;
} else if (status & SPIBAR_SSFS_DONE) {
break;
}
udelay(SPI_DELAY);
}
/* Flash protected range 0 register bit 31 indicates WP
* Bit 31[WPE] 1= WP Enable 0= WP Disable
*/ */
*sr = (read32(spibar + SPIBAR_FPR(0)) & SPIBAR_FPR_WPE) >> 24; ret = pch_hwseq_read_status(NULL, &rdsr);
if (ret) {
printk(BIOS_ERR, "SPI rdsr failed\n");
return ret;
}
*sr = rdsr & WPSR_MASK_SRP0_BIT;
return 0; return 0;
} }