ICH7 update
* change the code to use macros names instead of constants in many places * SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x) * SMI: Add support for mainboard GPI handler * SMI: immediate power-off on power button press, if OSPM is not active * Add fix for some USB errata * Some register tweaks for mobile systems * Enable configure SCI on interrupt 9 correctly. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
24b4df5f99
commit
7a3d095213
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@ -19,9 +19,9 @@
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* MA 02110-1301 USA
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*/
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Name(\_S0, Package(){0x0,0x0,0,0})
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Name(\_S1, Package(){0x1,0x0,0,0})
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Name(\_S3, Package(){0x5,0x0,0,0})
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Name(\_S4, Package(){0x6,0x0,0,0})
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Name(\_S5, Package(){0x7,0x0,0,0})
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Name(\_S0, Package(){0x0,0x0,0x0,0x0})
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// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
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Name(\_S3, Package(){0x5,0x5,0x0,0x0})
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Name(\_S4, Package(){0x6,0x6,0x0,0x0})
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Name(\_S5, Package(){0x7,0x7,0x0,0x0})
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@ -32,6 +32,8 @@
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/* TODO Make sure these don't get changed by stage2 */
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#define DEFAULT_GPIOBASE 0x0480
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#define DEFAULT_PMBASE 0x0500
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#define IO_APIC_ADDR 0xfec00000
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#define HPET_ADDR 0xfed00000
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#define DEFAULT_RCBA 0xfed1c000
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@ -276,7 +278,20 @@ extern void i82801gx_enable(device_t dev);
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/* ICH7 PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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@ -290,8 +305,24 @@ extern void i82801gx_enable(device_t dev);
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#define LV4 0x16
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#define PM2_CNT 0x20 // mobile only
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#define GPE0_STS 0x28
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#define USB4_STS (1 << 14)
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#define PME_B0_STS (1 << 13)
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#define USB3_STS (1 << 12)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define RI_STS (1 << 8)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define AC97_STS (1 << 5)
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#define USB2_STS (1 << 4)
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#define USB1_STS (1 << 3)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define THRM_STS (1 << 0)
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#define GPE0_EN 0x2c
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#define PME_B0_EN (1 << 13)
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#define PME_EN (1 << 11)
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#define SMI_EN 0x30
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#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
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#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
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@ -40,8 +40,8 @@ static void i82801gx_enable_apic(struct device *dev)
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{
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int i;
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
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volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
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volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
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volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
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/* Enable ACPI I/O and power management.
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* Set SCI IRQ to IRQ9
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@ -175,7 +175,7 @@ static void i82801gx_power_options(device_t dev)
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u8 reg8;
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u16 reg16, pmbase;
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u32 reg32;
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char *state;
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const char *state;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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@ -238,9 +238,13 @@ static void i82801gx_power_options(device_t dev)
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/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~((3 << 0) | (1 << 10));
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reg16 |= (1 << 3) | (1 << 5);
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reg16 |= (1 << 2); // CLKRUN_EN
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reg16 &= ~(3 << 0); // SMI# rate 1 minute
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reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only
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reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only
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reg16 |= (1 << 5); // CPUSLP_EN Desktop only
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// another laptop wants this?
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// reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
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reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
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* periodic SMIs.
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@ -259,15 +263,10 @@ static void i82801gx_power_options(device_t dev)
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/* Set up power management block and determine sleep mode */
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reg32 = inl(pmbase + 0x04); // PM1_CNT
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#if 0
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#if CONFIG_HAVE_ACPI_RESUME
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acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0;
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printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n",
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reg32, acpi_slp_type);
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#endif
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#endif
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reg32 &= ~(7 << 10); // SLP_TYP
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reg32 |= (1 << 1); // enable C3->C0 transition on bus master
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reg32 |= 1; // SCI_EN
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reg32 |= (1 << 0); // SCI_EN
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outl(reg32, pmbase + 0x04);
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}
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@ -308,10 +307,10 @@ static void enable_hpet(void)
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u32 reg32;
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/* Move HPET to default address 0xfed00000 and enable it */
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reg32 = RCBA32(0x3404);
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reg32 = RCBA32(HPTC);
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reg32 |= (1 << 7); // HPET Address Enable
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reg32 &= ~(3 << 0);
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RCBA32(0x3404) = reg32;
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RCBA32(HPTC) = reg32;
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}
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static void enable_clock_gating(void)
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@ -319,16 +318,18 @@ static void enable_clock_gating(void)
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u32 reg32;
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/* Enable Clock Gating for most devices */
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reg32 = RCBA32(0x341c);
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reg32 = RCBA32(CG);
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reg32 |= (1 << 31); // LPC clock gating
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reg32 |= (1 << 30); // PATA clock gating
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// SATA clock gating
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reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
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reg32 |= (1 << 23); // AC97 clock gating
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reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating
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reg32 |= (1 << 19); // USB EHCI clock gating
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reg32 |= (1 << 3) | (1 << 1); // DMI clock gating
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reg32 |= (1 << 2); // PCIe clock gating;
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RCBA32(0x341c) = reg32;
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reg32 &= ~(1 << 20); // No static clock gating for USB
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reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating
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RCBA32(CG) = reg32;
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}
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#if CONFIG_HAVE_SMI_HANDLER
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@ -392,10 +393,16 @@ static void i82801gx_spi_init(void)
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RCBA16(SPIBASE + 2) = spicontrol;
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}
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static void i82801gx_fixups(void)
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static void i82801gx_fixups(struct device *dev)
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{
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/* This needs to happen after PCI enumeration */
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RCBA32(0x1d40) |= 1;
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/* USB Transient Disconnect Detect:
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* Prevent a SE0 condition on the USB ports from being
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* interpreted by the UHCI controller as a disconnect
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*/
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pci_write_config8(dev, 0xad, 0x3);
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}
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static void lpc_init(struct device *dev)
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@ -437,7 +444,8 @@ static void lpc_init(struct device *dev)
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setup_i8259();
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/* The OS should do this? */
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// i8259_configure_irq_trigger(9, 1);
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/* Interrupt 9 should be level triggered (SCI) */
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i8259_configure_irq_trigger(9, 1);
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#if CONFIG_HAVE_SMI_HANDLER
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i82801gx_lock_smm(dev);
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@ -445,7 +453,7 @@ static void lpc_init(struct device *dev)
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i82801gx_spi_init();
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i82801gx_fixups();
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i82801gx_fixups(dev);
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}
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static void i82801gx_lpc_read_resources(device_t dev)
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@ -155,6 +155,34 @@ static void dump_gpe0_status(u32 gpe0_sts)
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printk_debug("\n");
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}
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/**
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* @brief read and clear ALT_GP_SMI_STS
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* @return ALT_GP_SMI_STS register
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*/
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static u16 reset_alt_gp_smi_status(void)
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{
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u16 reg16;
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reg16 = inl(pmbase + ALT_GP_SMI_STS);
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/* set status bits are cleared by writing 1 to them */
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outl(reg16, pmbase + ALT_GP_SMI_STS);
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return reg16;
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}
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static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
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{
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int i;
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printk_debug("ALT_GP_SMI_STS: ");
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for (i=15; i<= 0; i--) {
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if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16));
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}
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printk_debug("\n");
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}
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/**
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* @brief read and clear TCOx_STS
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* @return TCOx_STS registers
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@ -212,6 +240,7 @@ extern uint8_t smm_relocation_start, smm_relocation_end;
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void smm_relocate(void)
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{
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u32 smi_en;
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u16 pm1_en;
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printk_debug("Initializing SMM handler...");
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@ -232,6 +261,7 @@ void smm_relocate(void)
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dump_smi_status(reset_smi_status());
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dump_pm1_status(reset_pm1_status());
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dump_gpe0_status(reset_gpe0_status());
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dump_alt_gp_smi_status(reset_alt_gp_smi_status());
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dump_tco_status(reset_tco_status());
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/* Enable SMI generation:
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@ -244,6 +274,10 @@ void smm_relocate(void)
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*/
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smi_en = 0; /* reset SMI enables */
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#if 0
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smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
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#endif
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smi_en |= TCO_EN;
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smi_en |= APMC_EN;
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#if DEBUG_PERIODIC_SMIS
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@ -260,6 +294,11 @@ void smm_relocate(void)
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outl(smi_en, pmbase + SMI_EN);
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pm1_en = 0;
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pm1_en |= PWRBTN_EN;
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pm1_en |= GBL_EN;
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outw(pm1_en, pmbase + PM1_EN);
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/**
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* There are several methods of raising a controlled SMI# via
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* software, among them:
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@ -25,14 +25,15 @@
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_def.h>
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#include "i82801gx.h"
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#include "i82801gx_power.h"
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#define DEBUG_SMI
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#define APM_CNT 0xb2
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#define CST_CONTROL 0x85 // 0x85 crashes the box
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#define PST_CONTROL 0x80 // 0x80 crashes the box
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#define CST_CONTROL 0x85
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#define PST_CONTROL 0x80
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#define ACPI_DISABLE 0x1e
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#define ACPI_ENABLE 0xe1
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#define GNVS_UPDATE 0xea
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@ -88,6 +89,8 @@ static void dump_pm1_status(u16 pm1_sts)
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if (pm1_sts & (1 << 4)) printk_spew("BM ");
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if (pm1_sts & (1 << 0)) printk_spew("TMROF ");
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printk_spew("\n");
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int reg16 = inw(pmbase + PM1_EN);
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printk_spew("PM1_EN: %x\n", reg16);
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}
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/**
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@ -245,6 +248,41 @@ void southbridge_smi_set_eos(void)
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outb(reg8, pmbase + SMI_EN);
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}
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static void busmaster_disable_on_bus(int bus)
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{
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int slot, func;
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unsigned int val;
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unsigned char hdr;
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for (slot = 0; slot < 0x20; slot++) {
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for (func = 0; func < 8; func++) {
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u32 reg32;
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device_t dev = PCI_DEV(bus, slot, func);
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val = pci_read_config32(dev, PCI_VENDOR_ID);
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if (val == 0xffffffff || val == 0x00000000 ||
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val == 0x0000ffff || val == 0xffff0000)
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continue;
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/* Disable Bus Mastering for this one device */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 &= ~PCI_COMMAND_MASTER;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* If this is a bridge, then follow it. */
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hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
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hdr &= 0x7f;
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if (hdr == PCI_HEADER_TYPE_BRIDGE ||
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hdr == PCI_HEADER_TYPE_CARDBUS) {
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unsigned int buses;
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buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
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busmaster_disable_on_bus((buses >> 8) & 0xff);
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}
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}
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}
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}
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static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
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{
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@ -281,12 +319,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
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case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
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case 7:
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printk_debug("SMI#: Entering S5 (Soft Power off)\n");
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#if 0
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/* Set PME_B0_EN before going to S5 */
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reg32 = inl(pmbase + GPE0_EN);
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reg32 |= PME_B0_EN;
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outl(reg32, pmbase + GPE0_EN);
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#endif
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outl(0, pmbase + GPE0_EN);
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/* Should we keep the power state after a power loss?
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* In case the setting is "ON" or "OFF" we don't have
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* to do anything. But if it's "KEEP" we have to switch
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@ -297,6 +332,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
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reg8 |= 1;
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pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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}
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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break;
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default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break;
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}
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@ -376,6 +414,16 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_
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pm1_sts = reset_pm1_status();
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dump_pm1_status(pm1_sts);
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/* While OSPM is not active, poweroff immediately
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* on a power button event.
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*/
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if (pm1_sts & PWRBTN_STS) {
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// power button pressed
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u32 reg32;
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reg32 = (7 << 10) | (1 << 13);
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outl(reg32, pmbase + PM1_CNT);
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}
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}
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static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
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@ -386,6 +434,8 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state
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dump_gpe0_status(gpe0_sts);
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}
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void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
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static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
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{
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u16 reg16;
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@ -393,8 +443,13 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
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outl(reg16, pmbase + ALT_GP_SMI_STS);
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reg16 &= inw(pmbase + ALT_GP_SMI_EN);
|
||||
|
||||
if (mainboard_smi_gpi) {
|
||||
mainboard_smi_gpi(reg16);
|
||||
} else {
|
||||
if (reg16)
|
||||
printk_debug("GPI (mask %04x)\n",reg16);
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
|
||||
|
|
|
|||
|
|
@ -35,6 +35,10 @@ static void usb_init(struct device *dev)
|
|||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
|
||||
|
||||
// Erratum
|
||||
pci_write_config8(dev, 0xca, 0x00);
|
||||
|
||||
// Yes. Another Erratum
|
||||
reg8 = pci_read_config8(dev, 0xca);
|
||||
reg8 |= (1 << 0);
|
||||
pci_write_config8(dev, 0xca, reg8);
|
||||
|
|
|
|||
Loading…
Reference in New Issue