qualcomm: Add QCLib interface support to common/
Change-Id: I38d086c379a3c2f54d1603a2fed5b33860f7f4d7 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
T Michael Turney
Julius Werner
parent
32851c6df7
commit
7a3e46d767
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@ -0,0 +1,5 @@
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config QC_SDI_ENABLE
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bool
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default n
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prompt "Debug Build: enable SDI"
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@ -0,0 +1,31 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_MMU_COMMON_H_
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#define _SOC_QUALCOMM_MMU_COMMON_H_
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#include <commonlib/region.h>
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#include <soc/symbols_common.h>
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#define CACHED_RAM (MA_MEM | MA_S | MA_RW)
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#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC)
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#define DEV_MEM (MA_DEV | MA_S | MA_RW)
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static struct region * const ddr_region = (struct region *)_ddr_information;
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void soc_mmu_dram_config_post_dram_init(void);
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void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size);
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#endif /* _SOC_QUALCOMM_MMU_COMMON_H_ */
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@ -0,0 +1,76 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_QCLIB_COMMON_H__
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#define _SOC_QUALCOMM_QCLIB_COMMON_H__
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/* coreboot & QCLib I/F definitions */
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/* string field lengths */
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#define QCLIB_MAGIC_NUMBER_LENGTH 8
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#define QCLIB_FMAP_NAME_LENGTH 24
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#define QCLIB_TE_NAME_LENGTH 24
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/* FMAP_REGION names */
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#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING"
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#define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG"
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/* TE_NAME (table entry name) */
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#define QCLIB_TE_DDR_INFORMATION "ddr_information"
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#define QCLIB_TE_QCLIB_LOG_BUFFER "qclib_log_buffer"
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#define QCLIB_TE_DCB_SETTINGS "dcb_settings"
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#define QCLIB_TE_CDT_SETTINGS "cdt_settings"
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#define QCLIB_TE_PMIC_SETTINGS "pmic_settings"
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#define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data"
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#define QCLIB_TE_LIMITS_CFG_DATA "limits_cfg_data"
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#define QCLIB_TE_QCSDI "qcsdi"
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/* BA_BMASK_VALUES (blob_attributes bit mask values) */
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#define QCLIB_BA_SAVE_TO_STORAGE 0x00000001
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struct qclib_cb_if_table_entry {
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char name[QCLIB_TE_NAME_LENGTH]; /* 0x00 TE_NAME */
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uint64_t blob_address; /* 0x18 blob addr in SRAM */
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uint32_t size; /* 0x20 blob size in SRAM */
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uint32_t blob_attributes; /* 0x24 BA_BMASK_VALUES */
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};
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/* GA_BMASK_VALUES (global_attributes bit mask values) */
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#define QCLIB_GA_ENABLE_UART_LOGGING 0x00000001
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#define QCLIB_INTERFACE_VERSION 0x00000001
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#define QCLIB_MAX_NUMBER_OF_ENTRIES 16
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#define QCLIB_MAGIC_NUMBER "QCLIB_CB"
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struct qclib_cb_if_table {
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char magic[8]; /* 0x00 */
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uint32_t version; /* 0x08 */
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uint32_t num_entries; /* 0x0C */
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uint32_t max_entries; /* 0x10 */
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uint32_t global_attributes; /* 0x14 */
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uint64_t reserved; /* 0x18 */
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struct qclib_cb_if_table_entry
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te[QCLIB_MAX_NUMBER_OF_ENTRIES]; /* 0x20 */
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};
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extern struct qclib_cb_if_table qclib_cb_if_table;
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void qclib_add_if_table_entry(const char *name, void *base,
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uint32_t size, uint32_t attrs);
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void qclib_load_and_run(void);
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int qclib_soc_blob_load(void);
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#endif // _SOC_QUALCOMM_QCLIB_COMMON_H_
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_QUALCOMM_SYMBOLS_COMMON_H_
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#define _SOC_QUALCOMM_SYMBOLS_COMMON_H_
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#include <symbols.h>
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DECLARE_REGION(ddr_training);
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DECLARE_REGION(qclib_serial_log);
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DECLARE_REGION(ddr_information);
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#endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/mmu.h>
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#include <soc/mmu.h>
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#include <soc/mmu_common.h>
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__weak void soc_mmu_dram_config_post_dram_init(void) { /* no-op */ }
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void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size)
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{
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mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM);
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soc_mmu_dram_config_post_dram_init();
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/cbmem_console.h>
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#include <cbmem.h>
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#include <boardid.h>
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#include <fmap.h>
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#include <assert.h>
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#include <arch/mmu.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <soc/mmu.h>
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#include <soc/mmu_common.h>
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#include <soc/qclib_common.h>
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#include <soc/symbols_common.h>
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struct qclib_cb_if_table qclib_cb_if_table = {
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.magic = QCLIB_MAGIC_NUMBER,
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.version = QCLIB_INTERFACE_VERSION,
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.num_entries = 0,
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.max_entries = QCLIB_MAX_NUMBER_OF_ENTRIES,
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.global_attributes = 0,
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.reserved = 0,
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};
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void qclib_add_if_table_entry(const char *name, void *base,
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uint32_t size, uint32_t attrs)
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{
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struct qclib_cb_if_table_entry *te =
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&qclib_cb_if_table.te[qclib_cb_if_table.num_entries++];
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assert(qclib_cb_if_table.num_entries <= qclib_cb_if_table.max_entries);
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strncpy(te->name, name, sizeof(te->name));
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te->blob_address = (uintptr_t)base;
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te->size = size;
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te->blob_attributes = attrs;
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}
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static void write_ddr_information(struct qclib_cb_if_table_entry *te)
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{
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uint64_t ddr_size;
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/* Save DDR info in SRAM region to share with ramstage */
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ddr_region->offset = te->blob_address;
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ddr_size = te->size;
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ddr_region->size = ddr_size * MiB;
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/* Use DDR info to configure MMU */
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qc_mmu_dram_config_post_dram_init((void *)ddr_region->offset,
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(size_t)ddr_region->size);
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}
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static void write_qclib_log_to_cbmemc(struct qclib_cb_if_table_entry *te)
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{
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int i;
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char *ptr = (char *)te->blob_address;
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for (i = 0; i < te->size; i++)
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__cbmemc_tx_byte(*ptr++);
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}
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static void write_table_entry(struct qclib_cb_if_table_entry *te)
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{
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if (!strncmp(QCLIB_TE_DDR_INFORMATION, te->name,
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sizeof(te->name))) {
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write_ddr_information(te);
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} else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name,
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sizeof(te->name))) {
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assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA,
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(const void *)te->blob_address, te->size));
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} else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name,
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sizeof(te->name))) {
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assert(fmap_overwrite_area(QCLIB_FR_LIMITS_CFG_DATA,
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(const void *)te->blob_address, te->size));
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} else if (!strncmp(QCLIB_TE_QCLIB_LOG_BUFFER, te->name,
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sizeof(te->name))) {
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write_qclib_log_to_cbmemc(te);
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} else {
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printk(BIOS_WARNING, "%s write not implemented\n", te->name);
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printk(BIOS_WARNING, " blob_address[%llx]..size[%x]\n",
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te->blob_address, te->size);
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}
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}
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static void dump_te_table(void)
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{
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struct qclib_cb_if_table_entry *te;
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int i;
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for (i = 0; i < qclib_cb_if_table.num_entries; i++) {
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te = &qclib_cb_if_table.te[i];
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printk(BIOS_DEBUG, "[%s][%llx][%x][%x]\n",
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te->name, te->blob_address,
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te->size, te->blob_attributes);
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}
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}
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__weak int qclib_soc_blob_load(void) { return 0; }
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void qclib_load_and_run(void)
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{
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int i;
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ssize_t ssize;
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struct mmu_context pre_qclib_mmu_context;
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/* zero ddr_information SRAM region, needs new data each boot */
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memset(ddr_region, 0, sizeof(struct region));
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/* output area, QCLib copies console log buffer out */
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if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
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qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER,
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_qclib_serial_log,
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REGION_SIZE(qclib_serial_log), 0);
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/* output area, QCLib fills in DDR details */
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qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0);
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/* Attempt to load DDR Training Blob */
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ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training,
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REGION_SIZE(ddr_training));
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if (ssize < 0)
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goto fail;
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qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA,
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_ddr_training, ssize, 0);
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/* hook for SoC specific binary blob loads */
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if (qclib_soc_blob_load()) {
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printk(BIOS_ERR, "qclib_soc_blob_load failed\n");
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goto fail;
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}
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/* Enable QCLib serial output, based on Kconfig */
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if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
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qclib_cb_if_table.global_attributes =
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QCLIB_GA_ENABLE_UART_LOGGING;
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if (IS_ENABLED(CONFIG_QC_SDI_ENABLE)) {
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struct prog qcsdi =
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PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qcsdi");
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/* Attempt to load QCSDI elf */
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if (prog_locate(&qcsdi))
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goto fail;
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if (cbfs_prog_stage_load(&qcsdi))
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goto fail;
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qclib_add_if_table_entry(QCLIB_TE_QCSDI, prog_entry(&qcsdi),
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prog_size(&qcsdi), 0);
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printk(BIOS_INFO, "qcsdi.entry[%p]\n", qcsdi.entry);
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}
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dump_te_table();
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/* Attempt to load QCLib elf */
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struct prog qclib =
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PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qclib");
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if (prog_locate(&qclib))
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goto fail;
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if (cbfs_prog_stage_load(&qclib))
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goto fail;
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||||||
|
prog_set_entry(&qclib, prog_entry(&qclib), &qclib_cb_if_table);
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize DDR\n");
|
||||||
|
printk(BIOS_DEBUG, "Global Attributes[%x]..Table Entries Count[%d]\n",
|
||||||
|
qclib_cb_if_table.global_attributes,
|
||||||
|
qclib_cb_if_table.num_entries);
|
||||||
|
printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n",
|
||||||
|
prog_entry(&qclib), prog_entry_arg(&qclib));
|
||||||
|
|
||||||
|
/* back-up mmu context before disabling mmu and executing qclib */
|
||||||
|
mmu_save_context(&pre_qclib_mmu_context);
|
||||||
|
/* disable mmu before jumping to qclib. mmu_disable also
|
||||||
|
flushes and invalidates caches before disabling mmu. */
|
||||||
|
mmu_disable();
|
||||||
|
|
||||||
|
prog_run(&qclib);
|
||||||
|
|
||||||
|
/* Before returning, QCLib flushes cache and disables mmu.
|
||||||
|
Explicitly disable mmu (flush, invalidate and disable mmu)
|
||||||
|
before re-enabling mmu with backed-up mmu context */
|
||||||
|
mmu_disable();
|
||||||
|
mmu_restore_context(&pre_qclib_mmu_context);
|
||||||
|
mmu_enable();
|
||||||
|
|
||||||
|
/* step through I/F table, handling return values */
|
||||||
|
for (i = 0; i < qclib_cb_if_table.num_entries; i++)
|
||||||
|
if (qclib_cb_if_table.te[i].blob_attributes &
|
||||||
|
QCLIB_BA_SAVE_TO_STORAGE)
|
||||||
|
write_table_entry(&qclib_cb_if_table.te[i]);
|
||||||
|
|
||||||
|
/* confirm that we received valid ddr information from QCLib */
|
||||||
|
assert((uintptr_t)_dram == region_offset(ddr_region) &&
|
||||||
|
region_sz(ddr_region) >= (u8 *)cbmem_top() - _dram);
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "QCLib completed\n\n\n");
|
||||||
|
|
||||||
|
return;
|
||||||
|
|
||||||
|
fail:
|
||||||
|
die("Couldn't run QCLib.\n");
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue