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- Modify the freebios tree so the pci config space api is mostly in sync between 

code that runs without ram and code that runs with ram.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2003-06-12 19:23:51 +00:00
parent 540ae01cd3
commit 7a5416af95
9 changed files with 174 additions and 226 deletions
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51
src/arch/i386/include/arch/romcc_io.h
View File

@ -61,56 +61,6 @@ static void wrmsr(unsigned long index, msr_t msr)
#define PCI_ID(VENDOR_ID, DEVICE_ID) \ #define PCI_ID(VENDOR_ID, DEVICE_ID) \
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
#if 0
static unsigned char pci_read_config8(unsigned addr)
{
outl(0x80000000 | (addr & ~3), 0xCF8);
return inb(0xCFC + (addr & 3));
}
static unsigned short pci_read_config16(unsigned addr)
{
outl(0x80000000 | (addr & ~3), 0xCF8);
return inw(0xCFC + (addr & 2));
}
static unsigned int pci_read_config32(unsigned addr)
{
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}
static void pci_write_config8(unsigned addr, unsigned char value)
{
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
}
static void pci_write_config16(unsigned addr, unsigned short value)
{
outl(0x80000000 | (addr & ~3), 0xCF8);
outw(value, 0xCFC + (addr & 2));
}
static void pci_write_config32(unsigned addr, unsigned int value)
{
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
}
static unsigned pci_locate_device(unsigned pci_id, unsigned addr)
{
addr &= ~0xff;
for(; addr <= PCI_ADDR(255, 31, 7, 0); addr += PCI_ADDR(0,0,1,0)) {
unsigned int id;
id = pci_read_config32(addr);
if (id == pci_id) {
return addr;
}
}
return ~0U;
}
#else
typedef unsigned device_t; typedef unsigned device_t;
static unsigned char pci_read_config8(device_t dev, unsigned where) static unsigned char pci_read_config8(device_t dev, unsigned where)
@ -174,4 +124,3 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev)
return PCI_DEV_INVALID; return PCI_DEV_INVALID;
} }
#endif

163
src/arch/i386/lib/pci_ops.c
View File

@ -7,12 +7,12 @@
static const struct pci_ops *conf; static const struct pci_ops *conf;
struct pci_ops { struct pci_ops {
int (*read_byte) (uint8_t bus, int devfn, int where, uint8_t * val); uint8_t (*read8) (uint8_t bus, int devfn, int where);
int (*read_word) (uint8_t bus, int devfn, int where, uint16_t * val); uint16_t (*read16) (uint8_t bus, int devfn, int where);
int (*read_dword) (uint8_t bus, int devfn, int where, uint32_t * val); uint32_t (*read32) (uint8_t bus, int devfn, int where);
int (*write_byte) (uint8_t bus, int devfn, int where, uint8_t val); void (*write8) (uint8_t bus, int devfn, int where, uint8_t val);
int (*write_word) (uint8_t bus, int devfn, int where, uint16_t val); void (*write16) (uint8_t bus, int devfn, int where, uint16_t val);
int (*write_dword) (uint8_t bus, int devfn, int where, uint32_t val); void (*write32) (uint8_t bus, int devfn, int where, uint32_t val);
}; };
/* /*
@ -26,58 +26,52 @@ struct pci_ops {
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)) #define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
static int pci_conf1_read_config_byte(unsigned char bus, int devfn, int where, uint8_t * value) static uint8_t pci_conf1_read_config8(unsigned char bus, int devfn, int where)
{ {
outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
*value = inb(0xCFC + (where & 3)); return inb(0xCFC + (where & 3));
return 0;
} }
static int pci_conf1_read_config_word(unsigned char bus, int devfn, int where, uint16_t * value) static uint16_t pci_conf1_read_config16(unsigned char bus, int devfn, int where)
{ {
outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
*value = inw(0xCFC + (where & 2)); return inw(0xCFC + (where & 2));
return 0;
} }
static int pci_conf1_read_config_dword(unsigned char bus, int devfn, int where, uint32_t * value) static uint32_t pci_conf1_read_config32(unsigned char bus, int devfn, int where)
{ {
outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
*value = inl(0xCFC); return inl(0xCFC);
return 0;
} }
static int pci_conf1_write_config_byte(unsigned char bus, int devfn, int where, uint8_t value) static void pci_conf1_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
{ {
outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outb(value, 0xCFC + (where & 3)); outb(value, 0xCFC + (where & 3));
return 0;
} }
static int pci_conf1_write_config_word(unsigned char bus, int devfn, int where, uint16_t value) static void pci_conf1_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
{ {
outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outw(value, 0xCFC + (where & 2)); outw(value, 0xCFC + (where & 2));
return 0;
} }
static int pci_conf1_write_config_dword(unsigned char bus, int devfn, int where, uint32_t value) static void pci_conf1_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
{ {
outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(CONFIG_CMD(bus, devfn, where), 0xCF8);
outl(value, 0xCFC); outl(value, 0xCFC);
return 0;
} }
#undef CONFIG_CMD #undef CONFIG_CMD
static const struct pci_ops pci_direct_conf1 = static const struct pci_ops pci_direct_conf1 =
{ {
pci_conf1_read_config_byte, .read8 = pci_conf1_read_config8,
pci_conf1_read_config_word, .read16 = pci_conf1_read_config16,
pci_conf1_read_config_dword, .read32 = pci_conf1_read_config32,
pci_conf1_write_config_byte, .write8 = pci_conf1_write_config8,
pci_conf1_write_config_word, .write16 = pci_conf1_write_config16,
pci_conf1_write_config_dword .write32 = pci_conf1_write_config32,
}; };
/* /*
@ -86,54 +80,54 @@ static const struct pci_ops pci_direct_conf1 =
#define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where) #define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
#define FUNC(devfn) (((devfn & 7) << 1) | 0xf0) #define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
#define SET(bus,devfn) if (devfn & 0x80) return -1;outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA); #define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
static int pci_conf2_read_config_byte(unsigned char bus, int devfn, int where, uint8_t * value) static uint8_t pci_conf2_read_config8(unsigned char bus, int devfn, int where)
{ {
uint8_t value;
SET(bus, devfn); SET(bus, devfn);
*value = inb(IOADDR(devfn, where)); value = inb(IOADDR(devfn, where));
outb(0, 0xCF8); outb(0, 0xCF8);
return 0; return value;
} }
static int pci_conf2_read_config_word(unsigned char bus, int devfn, int where, uint16_t * value) static uint16_t pci_conf2_read_config16(unsigned char bus, int devfn, int where)
{ {
uint16_t value;
SET(bus, devfn); SET(bus, devfn);
*value = inw(IOADDR(devfn, where)); value = inw(IOADDR(devfn, where));
outb(0, 0xCF8); outb(0, 0xCF8);
return 0; return value;
} }
static int pci_conf2_read_config_dword(unsigned char bus, int devfn, int where, uint32_t * value) static uint32_t pci_conf2_read_config32(unsigned char bus, int devfn, int where)
{ {
uint32_t value;
SET(bus, devfn); SET(bus, devfn);
*value = inl(IOADDR(devfn, where)); value = inl(IOADDR(devfn, where));
outb(0, 0xCF8); outb(0, 0xCF8);
return 0; return value;
} }
static int pci_conf2_write_config_byte(unsigned char bus, int devfn, int where, uint8_t value) static void pci_conf2_write_config8(unsigned char bus, int devfn, int where, uint8_t value)
{ {
SET(bus, devfn); SET(bus, devfn);
outb(value, IOADDR(devfn, where)); outb(value, IOADDR(devfn, where));
outb(0, 0xCF8); outb(0, 0xCF8);
return 0;
} }
static int pci_conf2_write_config_word(unsigned char bus, int devfn, int where, uint16_t value) static void pci_conf2_write_config16(unsigned char bus, int devfn, int where, uint16_t value)
{ {
SET(bus, devfn); SET(bus, devfn);
outw(value, IOADDR(devfn, where)); outw(value, IOADDR(devfn, where));
outb(0, 0xCF8); outb(0, 0xCF8);
return 0;
} }
static int pci_conf2_write_config_dword(unsigned char bus, int devfn, int where, uint32_t value) static void pci_conf2_write_config32(unsigned char bus, int devfn, int where, uint32_t value)
{ {
SET(bus, devfn); SET(bus, devfn);
outl(value, IOADDR(devfn, where)); outl(value, IOADDR(devfn, where));
outb(0, 0xCF8); outb(0, 0xCF8);
return 0;
} }
#undef SET #undef SET
@ -142,12 +136,12 @@ static int pci_conf2_write_config_dword(unsigned char bus, int devfn, int where,
static const struct pci_ops pci_direct_conf2 = static const struct pci_ops pci_direct_conf2 =
{ {
pci_conf2_read_config_byte, .read8 = pci_conf2_read_config8,
pci_conf2_read_config_word, .read16 = pci_conf2_read_config16,
pci_conf2_read_config_dword, .read32 = pci_conf2_read_config32,
pci_conf2_write_config_byte, .write8 = pci_conf2_write_config8,
pci_conf2_write_config_word, .write16 = pci_conf2_write_config16,
pci_conf2_write_config_dword .write32 = pci_conf2_write_config32,
}; };
/* /*
@ -162,7 +156,7 @@ static const struct pci_ops pci_direct_conf2 =
*/ */
static int pci_sanity_check(const struct pci_ops *o) static int pci_sanity_check(const struct pci_ops *o)
{ {
uint16_t x; uint16_t class, vendor;
uint8_t bus; uint8_t bus;
int devfn; int devfn;
#define PCI_CLASS_BRIDGE_HOST 0x0600 #define PCI_CLASS_BRIDGE_HOST 0x0600
@ -171,12 +165,15 @@ static int pci_sanity_check(const struct pci_ops *o)
#define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_VENDOR_ID_INTEL 0x8086
#define PCI_VENDOR_ID_MOTOROLA 0x1057 #define PCI_VENDOR_ID_MOTOROLA 0x1057
for (bus = 0, devfn = 0; devfn < 0x100; devfn++) for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
if ((!o->read_word(bus, devfn, PCI_CLASS_DEVICE, &x) && class = o->read16(bus, devfn, PCI_CLASS_DEVICE);
(x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) || vendor = o->read16(bus, devfn, PCI_VENDOR_ID);
(!o->read_word(bus, devfn, PCI_VENDOR_ID, &x) && if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
(x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ || x == PCI_VENDOR_ID_MOTOROLA))) ((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
(vendor == PCI_VENDOR_ID_MOTOROLA))) {
return 1; return 1;
}
}
printk_err("PCI: Sanity check failed\n"); printk_err("PCI: Sanity check failed\n");
return 0; return 0;
} }
@ -220,54 +217,52 @@ static const struct pci_ops *pci_check_direct(void)
return 0; return 0;
} }
int pci_read_config_byte(struct device *dev, uint8_t where, uint8_t * val) uint8_t pci_read_config8(device_t dev, unsigned where)
{ {
int res; uint8_t value;
res = conf->read_byte(dev->bus->secondary, dev->devfn, where, val); value = conf->read8(dev->bus->secondary, dev->devfn, where);
printk_spew("Read config byte bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", printk_spew("Read config 8 bus %d,devfn 0x%x,reg 0x%x,val 0x%x\n",
dev->bus->secondary, dev->devfn, where, *val, res); dev->bus->secondary, dev->devfn, where, value);
return res; return value;
} }
int pci_read_config_word(struct device *dev, uint8_t where, uint16_t * val) uint16_t pci_read_config16(device_t dev, unsigned where)
{ {
int res; uint16_t value;
res = conf->read_word(dev->bus->secondary, dev->devfn, where, val); value = conf->read16(dev->bus->secondary, dev->devfn, where);
printk_spew( "Read config word bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", printk_spew( "Read config 16 bus %d,devfn 0x%x,reg 0x%x,val 0x%x\n",
dev->bus->secondary, dev->devfn, where, *val, res); dev->bus->secondary, dev->devfn, where, value);
return res; return value;
} }
int pci_read_config_dword(struct device *dev, uint8_t where, uint32_t * val) uint32_t pci_read_config32(device_t dev, unsigned where)
{ {
int res; uint32_t value;
res = conf->read_dword(dev->bus->secondary, dev->devfn, where, val); value = conf->read32(dev->bus->secondary, dev->devfn, where);
printk_spew( "Read config dword bus %d,devfn 0x%x,reg 0x%x,val 0x%x,res 0x%x\n", printk_spew( "Read config 32 bus %d,devfn 0x%x,reg 0x%x,val 0x%x\n",
dev->bus->secondary, dev->devfn, where, *val, res); dev->bus->secondary, dev->devfn, where, *val);
return res; return value;
} }
int pci_write_config_byte(struct device *dev, uint8_t where, uint8_t val) void pci_write_config8(device_t dev, unsigned where, uint8_t val)
{ {
printk_spew( "Write config byte bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", printk_spew( "Write config 8 bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n",
dev->bus->secondary, dev->devfn, where, val); dev->bus->secondary, dev->devfn, where, val);
return conf->write_byte(dev->bus->secondary, dev->devfn, where, val); conf->write8(dev->bus->secondary, dev->devfn, where, val);
} }
int pci_write_config_word(struct device *dev, uint8_t where, uint16_t val) void pci_write_config16(device_t dev, unsigned where, uint16_t val)
{ {
printk_spew( "Write config word bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", printk_spew( "Write config 16 bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n",
dev->bus->secondary, dev->devfn, where, val); dev->bus->secondary, dev->devfn, where, val);
return conf->write_word(dev->bus->secondary, dev->devfn, where, val); conf->write16(dev->bus->secondary, dev->devfn, where, val);
} }
int pci_write_config_dword(struct device *dev, uint8_t where, uint32_t val) void pci_write_config32(device_t dev, unsigned where, uint32_t val)
{ {
printk_spew( "Write config dword bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n", printk_spew( "Write config 32 bus %d, devfn 0x%x, reg 0x%x, val 0x%x\n",
dev->bus->secondary, dev->devfn, where, val); dev->bus->secondary, dev->devfn, where, val);
return conf->write_dword(dev->bus->secondary, dev->devfn, where, val); conf->write32(dev->bus->secondary, dev->devfn, where, val);
} }
/** Set the method to be used for PCI, type I or type II /** Set the method to be used for PCI, type I or type II

10
src/devices/device.c
View File

@ -274,7 +274,7 @@ static void allocate_vga_resource(void)
bus = vga = 0; bus = vga = 0;
for(dev = all_devices; dev; dev = dev->next) { for(dev = all_devices; dev; dev = dev->next) {
uint32_t class_revision; uint32_t class_revision;
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_revision); class_revision = pci_read_config32(dev, PCI_CLASS_REVISION);
if (((class_revision >> 24) == 0x03) && if (((class_revision >> 24) == 0x03) &&
((class_revision >> 16) != 0x380)) { ((class_revision >> 16) != 0x380)) {
if (!vga) { if (!vga) {
@ -296,9 +296,9 @@ static void allocate_vga_resource(void)
/* Now walk up the bridges setting the VGA enable */ /* Now walk up the bridges setting the VGA enable */
while(bus) { while(bus) {
uint16_t ctrl; uint16_t ctrl;
pci_read_config_word(bus, PCI_BRIDGE_CONTROL, &ctrl); ctrl = pci_read_config16(bus, PCI_BRIDGE_CONTROL);
ctrl |= PCI_BRIDGE_CTL_VGA; ctrl |= PCI_BRIDGE_CTL_VGA;
pci_write_config_word(bus, PCI_BRIDGE_CONTROL, ctrl); pci_write_config16(bus, PCI_BRIDGE_CONTROL, ctrl);
bus = (bus == bus->bus)? 0 : bus->bus; bus = (bus == bus->bus)? 0 : bus->bus;
} }
} }
@ -331,13 +331,13 @@ static void enable_resources(struct device *bus)
*/ */
for (curdev = all_devices; curdev; curdev = curdev->next) { for (curdev = all_devices; curdev; curdev = curdev->next) {
uint16_t command; uint16_t command;
pci_read_config_word(curdev, PCI_COMMAND, &command); command = pci_read_config16(curdev, PCI_COMMAND);
command |= curdev->command; command |= curdev->command;
printk_debug("DEV: %02x:%02x.%01x cmd <- %02x\n", printk_debug("DEV: %02x:%02x.%01x cmd <- %02x\n",
curdev->bus->secondary, curdev->bus->secondary,
PCI_SLOT(curdev->devfn), PCI_FUNC(curdev->devfn), PCI_SLOT(curdev->devfn), PCI_FUNC(curdev->devfn),
command); command);
pci_write_config_word(curdev, PCI_COMMAND, command); pci_write_config16(curdev, PCI_COMMAND, command);
} }
} }

100
src/devices/pci_device.c
View File

@ -18,8 +18,6 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
static unsigned int pci_scan_bridge(struct device *bus, unsigned int max);
/** Given a device and register, read the size of the BAR for that register. /** Given a device and register, read the size of the BAR for that register.
* @param dev Pointer to the device structure * @param dev Pointer to the device structure
* @param resource Pointer to the resource structure * @param resource Pointer to the resource structure
@ -39,7 +37,7 @@ static void pci_get_resource(struct device *dev, struct resource *resource, unsi
resource->flags = 0; resource->flags = 0;
resource->index = index; resource->index = index;
pci_read_config_dword(dev, index, &addr); addr = pci_read_config32(dev, index);
if (addr == 0xffffffffUL) if (addr == 0xffffffffUL)
return; return;
@ -48,15 +46,15 @@ static void pci_get_resource(struct device *dev, struct resource *resource, unsi
* treat them as 32-bit resources * treat them as 32-bit resources
*/ */
/* get the size */ /* get the size */
pci_write_config_dword(dev, index, ~0); pci_write_config32(dev, index, ~0);
pci_read_config_dword(dev, index, &size); size = pci_read_config32(dev, index);
/* get the minimum value the bar can be set to */ /* get the minimum value the bar can be set to */
pci_write_config_dword(dev, index, 0); pci_write_config32(dev, index, 0);
pci_read_config_dword(dev, index, &base); base = pci_read_config32(dev, index);
/* restore addr */ /* restore addr */
pci_write_config_dword(dev, index, addr); pci_write_config32(dev, index, addr);
/* /*
* some broken hardware has read-only registers that do not * some broken hardware has read-only registers that do not
@ -118,21 +116,21 @@ static void pci_get_resource(struct device *dev, struct resource *resource, unsi
index_hi = index + 4; index_hi = index + 4;
resource->limit = 0xffffffffUL; resource->limit = 0xffffffffUL;
resource->flags |= IORESOURCE_PCI64; resource->flags |= IORESOURCE_PCI64;
pci_read_config_dword( dev, index_hi, &addr); addr = pci_read_config32( dev, index_hi);
/* get the extended size */ /* get the extended size */
pci_write_config_dword(dev, index_hi, 0xffffffffUL); pci_write_config32(dev, index_hi, 0xffffffffUL);
pci_read_config_dword( dev, index_hi, &size); size = pci_read_config32( dev, index_hi);
/* get the minimum value the bar can be set to */ /* get the minimum value the bar can be set to */
pci_write_config_dword(dev, index_hi, 0); pci_write_config32(dev, index_hi, 0);
pci_read_config_dword(dev, index_hi, &base); base = pci_read_config32(dev, index_hi);
/* restore addr */ /* restore addr */
pci_write_config_dword(dev, index_hi, addr); pci_write_config32(dev, index_hi, addr);
if ((size == 0xffffffff) && (base == 0)) { if ((size == 0xffffffff) && (base == 0)) {
/* Clear the top half of the bar */ /* Clear the top half of the bar */
pci_write_config_dword(dev, index_hi, 0); pci_write_config32(dev, index_hi, 0);
} }
else { else {
printk_err("PCI: %02x:%02x.%01x Unable to handle 64-bit address\n", printk_err("PCI: %02x:%02x.%01x Unable to handle 64-bit address\n",
@ -226,7 +224,7 @@ void pci_dev_read_resources(struct device *dev)
dev->resources = 0; dev->resources = 0;
memset(&dev->resource[0], 0, sizeof(dev->resource)); memset(&dev->resource[0], 0, sizeof(dev->resource));
pci_read_bases(dev, 6); pci_read_bases(dev, 6);
pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr); addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
dev->rom_address = (addr == 0xffffffff)? 0 : addr; dev->rom_address = (addr == 0xffffffff)? 0 : addr;
} }
@ -238,7 +236,7 @@ void pci_bus_read_resources(struct device *dev)
pci_bridge_read_bases(dev); pci_bridge_read_bases(dev);
pci_read_bases(dev, 2); pci_read_bases(dev, 2);
pci_read_config_dword(dev, PCI_ROM_ADDRESS1, &addr); addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
dev->rom_address = (addr == 0xffffffff)? 0 : addr; dev->rom_address = (addr == 0xffffffff)? 0 : addr;
} }
@ -291,10 +289,10 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
if (resource->flags & IORESOURCE_IO) { if (resource->flags & IORESOURCE_IO) {
base |= PCI_BASE_ADDRESS_SPACE_IO; base |= PCI_BASE_ADDRESS_SPACE_IO;
} }
pci_write_config_dword(dev, resource->index, base & 0xffffffff); pci_write_config32(dev, resource->index, base & 0xffffffff);
if (resource->flags & IORESOURCE_PCI64) { if (resource->flags & IORESOURCE_PCI64) {
/* FIXME handle real 64bit base addresses */ /* FIXME handle real 64bit base addresses */
pci_write_config_dword(dev, resource->index + 4, 0); pci_write_config32(dev, resource->index + 4, 0);
} }
} }
else if (resource->index == PCI_IO_BASE) { else if (resource->index == PCI_IO_BASE) {
@ -303,8 +301,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
*/ */
compute_allocate_resource(dev, resource, compute_allocate_resource(dev, resource,
IORESOURCE_IO, IORESOURCE_IO); IORESOURCE_IO, IORESOURCE_IO);
pci_write_config_byte(dev, PCI_IO_BASE, base >> 8); pci_write_config8(dev, PCI_IO_BASE, base >> 8);
pci_write_config_byte(dev, PCI_IO_LIMIT, limit >> 8); pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
} }
else if (resource->index == PCI_MEMORY_BASE) { else if (resource->index == PCI_MEMORY_BASE) {
/* set the memory range /* set the memory range
@ -312,8 +310,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
compute_allocate_resource(dev, resource, compute_allocate_resource(dev, resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM); IORESOURCE_MEM);
pci_write_config_word(dev, PCI_MEMORY_BASE, base >> 16); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
pci_write_config_word(dev, PCI_MEMORY_LIMIT, limit >> 16); pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
} }
else if (resource->index == PCI_PREF_MEMORY_BASE) { else if (resource->index == PCI_PREF_MEMORY_BASE) {
/* set the prefetchable memory range /* set the prefetchable memory range
@ -322,8 +320,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
compute_allocate_resource(dev, resource, compute_allocate_resource(dev, resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH); IORESOURCE_MEM | IORESOURCE_PREFETCH);
pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, base >> 16); pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16); pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
} }
else { else {
printk_err("ERROR: invalid resource->index %x\n", printk_err("ERROR: invalid resource->index %x\n",
@ -361,20 +359,20 @@ void pci_dev_set_resources(struct device *dev)
} }
/* set a default latency timer */ /* set a default latency timer */
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
/* set a default secondary latency timer */ /* set a default secondary latency timer */
if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
} }
/* zero the irq settings */ /* zero the irq settings */
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &line); line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
if (line) { if (line) {
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
} }
/* set the cache line size, so far 64 bytes is good for everyone */ /* set the cache line size, so far 64 bytes is good for everyone */
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
} }
struct device_operations default_pci_ops_dev = { struct device_operations default_pci_ops_dev = {
@ -494,12 +492,12 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
dummy.bus = bus; dummy.bus = bus;
dummy.devfn = 0; dummy.devfn = 0;
pci_read_config_dword(&dummy, PCI_VENDOR_ID, &id); id = pci_read_config32(&dummy, PCI_VENDOR_ID);
if (id == 0xffffffff || id == 0x00000000 || if (id == 0xffffffff || id == 0x00000000 ||
id == 0x0000ffff || id == 0xffff0000) { id == 0x0000ffff || id == 0xffff0000) {
break; break;
} }
pci_read_config_byte(&dummy, PCI_HEADER_TYPE, &hdr_type); hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
pos = 0; pos = 0;
switch(hdr_type & 0x7f) { switch(hdr_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL: case PCI_HEADER_TYPE_NORMAL:
@ -508,15 +506,15 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
break; break;
} }
if (pos > PCI_CAP_LIST_NEXT) { if (pos > PCI_CAP_LIST_NEXT) {
pci_read_config_byte(&dummy, pos, &pos); pos = pci_read_config8(&dummy, pos);
} }
while(pos != 0) { while(pos != 0) {
uint8_t cap; uint8_t cap;
pci_read_config_byte(&dummy, pos + PCI_CAP_LIST_ID, &cap); cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos); printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
if (cap == PCI_CAP_ID_HT) { if (cap == PCI_CAP_ID_HT) {
uint16_t flags; uint16_t flags;
pci_read_config_word(&dummy, pos + PCI_CAP_FLAGS, &flags); flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
printk_debug("flags: 0x%04x\n", (unsigned)flags); printk_debug("flags: 0x%04x\n", (unsigned)flags);
if ((flags >> 13) == 0) { if ((flags >> 13) == 0) {
unsigned count; unsigned count;
@ -525,12 +523,12 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
count = (flags >> 5) & 0x1f; count = (flags >> 5) & 0x1f;
printk_debug("unitid: 0x%02x, count: 0x%02x\n", printk_debug("unitid: 0x%02x, count: 0x%02x\n",
next_unitid, count); next_unitid, count);
pci_write_config_word(&dummy, pos + PCI_CAP_FLAGS, flags); pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
next_unitid += count; next_unitid += count;
break; break;
} }
} }
pci_read_config_byte(&dummy, pos + PCI_CAP_LIST_NEXT, &pos); pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
} }
} while((last_unitid != next_unitid) && (next_unitid <= 0x1f)); } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
#endif /* HYPERTRANSPORT_SUPPORT */ #endif /* HYPERTRANSPORT_SUPPORT */
@ -547,7 +545,7 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
dummy.bus = bus; dummy.bus = bus;
dummy.devfn = devfn; dummy.devfn = devfn;
pci_read_config_dword(&dummy, PCI_VENDOR_ID, &id); id = pci_read_config32(&dummy, PCI_VENDOR_ID);
/* some broken boards return 0 if a slot is empty: */ /* some broken boards return 0 if a slot is empty: */
if (!dev && if (!dev &&
(id == 0xffffffff || id == 0x00000000 || (id == 0xffffffff || id == 0x00000000 ||
@ -561,8 +559,8 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
/* multi function device, skip to next function */ /* multi function device, skip to next function */
continue; continue;
} }
pci_read_config_byte(&dummy, PCI_HEADER_TYPE, &hdr_type); hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
pci_read_config_dword(&dummy, PCI_CLASS_REVISION, &class); class = pci_read_config32(&dummy, PCI_CLASS_REVISION);
if (!dev) { if (!dev) {
if ((dev = malloc(sizeof(*dev))) == 0) { if ((dev = malloc(sizeof(*dev))) == 0) {
@ -581,12 +579,12 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
dev->class = class >> 8; dev->class = class >> 8;
/* non-destructively determine if device can be a master: */ /* non-destructively determine if device can be a master: */
pci_read_config_byte(dev, PCI_COMMAND, &cmd); cmd = pci_read_config8(dev, PCI_COMMAND);
pci_write_config_byte(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); pci_write_config8(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
pci_read_config_byte(dev, PCI_COMMAND, &tmp); tmp = pci_read_config8(dev, PCI_COMMAND);
dev->master = ((tmp & PCI_COMMAND_MASTER) != 0); dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
pci_write_config_byte(dev, PCI_COMMAND, cmd); pci_write_config8(dev, PCI_COMMAND, cmd);
/* Look at the vendor and device id, or at least the /* Look at the vendor and device id, or at least the
* header type and class and figure out which set of configuration * header type and class and figure out which set of configuration
@ -651,15 +649,15 @@ unsigned int pci_scan_bridge(struct device *bus, unsigned int max)
bus->subordinate = 0xff; bus->subordinate = 0xff;
/* Clear all status bits and turn off memory, I/O and master enables. */ /* Clear all status bits and turn off memory, I/O and master enables. */
pci_read_config_word(bus, PCI_COMMAND, &cr); cr = pci_read_config16(bus, PCI_COMMAND);
pci_write_config_word(bus, PCI_COMMAND, 0x0000); pci_write_config16(bus, PCI_COMMAND, 0x0000);
pci_write_config_word(bus, PCI_STATUS, 0xffff); pci_write_config16(bus, PCI_STATUS, 0xffff);
/* /*
* Read the existing primary/secondary/subordinate bus * Read the existing primary/secondary/subordinate bus
* number configuration. * number configuration.
*/ */
pci_read_config_dword(bus, PCI_PRIMARY_BUS, &buses); buses = pci_read_config32(bus, PCI_PRIMARY_BUS);
/* Configure the bus numbers for this bridge: the configuration /* Configure the bus numbers for this bridge: the configuration
* transactions will not be propagated by the bridge if it is not * transactions will not be propagated by the bridge if it is not
@ -669,7 +667,7 @@ unsigned int pci_scan_bridge(struct device *bus, unsigned int max)
buses |= (((unsigned int) (bus->bus->secondary) << 0) | buses |= (((unsigned int) (bus->bus->secondary) << 0) |
((unsigned int) (bus->secondary) << 8) | ((unsigned int) (bus->secondary) << 8) |
((unsigned int) (bus->subordinate) << 16)); ((unsigned int) (bus->subordinate) << 16));
pci_write_config_dword(bus, PCI_PRIMARY_BUS, buses); pci_write_config32(bus, PCI_PRIMARY_BUS, buses);
/* Now we can scan all subordinate buses i.e. the bus hehind the bridge */ /* Now we can scan all subordinate buses i.e. the bus hehind the bridge */
max = pci_scan_bus(bus, max); max = pci_scan_bus(bus, max);
@ -680,8 +678,8 @@ unsigned int pci_scan_bridge(struct device *bus, unsigned int max)
bus->subordinate = max; bus->subordinate = max;
buses = (buses & 0xff00ffff) | buses = (buses & 0xff00ffff) |
((unsigned int) (bus->subordinate) << 16); ((unsigned int) (bus->subordinate) << 16);
pci_write_config_dword(bus, PCI_PRIMARY_BUS, buses); pci_write_config32(bus, PCI_PRIMARY_BUS, buses);
pci_write_config_word(bus, PCI_COMMAND, cr); pci_write_config16(bus, PCI_COMMAND, cr);
return max; return max;
} }

30
src/include/device/device.h
View File

@ -4,11 +4,13 @@
#include <device/resource.h> #include <device/resource.h>
struct device; struct device;
typedef struct device * device_t;
struct device_operations { struct device_operations {
void (*read_resources)(struct device *dev); void (*read_resources)(device_t dev);
void (*set_resources)(struct device *dev); void (*set_resources)(device_t dev);
void (*init)(struct device *dev); void (*init)(device_t dev);
unsigned int (*scan_bus)(struct device *bus, unsigned int max); unsigned int (*scan_bus)(device_t bus, unsigned int max);
}; };
@ -19,10 +21,10 @@ struct device_operations {
*/ */
struct device { struct device {
struct device *bus; /* bus this device is on */ device_t bus; /* bus this device is on */
struct device *children; /* devices behind this bridge */ device_t children; /* devices behind this bridge */
struct device *sibling; /* next device on this bus */ device_t sibling; /* next device on this bus */
struct device *next; /* chain of all devices */ device_t next; /* chain of all devices */
unsigned int devfn; /* encoded device & function index */ unsigned int devfn; /* encoded device & function index */
unsigned short vendor; unsigned short vendor;
@ -68,18 +70,18 @@ extern void dev_enable(void);
extern void dev_initialize(void); extern void dev_initialize(void);
/* Generic device helper functions */ /* Generic device helper functions */
void append_device(struct device *dev); void append_device(device_t dev);
void compute_allocate_resource(struct device *bus, struct resource *bridge, void compute_allocate_resource(device_t bus, struct resource *bridge,
unsigned long type_mask, unsigned long type); unsigned long type_mask, unsigned long type);
void assign_resources(struct device *bus); void assign_resources(device_t bus);
void enumerate_static_device(void); void enumerate_static_device(void);
unsigned long device_memory_base; unsigned long device_memory_base;
/* Helper functions */ /* Helper functions */
struct device *dev_find_device (unsigned int vendor, unsigned int device, struct device *from); device_t dev_find_device (unsigned int vendor, unsigned int device, device_t from);
struct device *dev_find_class (unsigned int class, struct device *from); device_t dev_find_class (unsigned int class, device_t from);
struct device *dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot (unsigned int bus, unsigned int devfn);
/* Rounding for boundaries. /* Rounding for boundaries.
* Due to some chip bugs, go ahead and roung IO to 16 * Due to some chip bugs, go ahead and roung IO to 16

15
src/include/device/pci_ops.h
View File

@ -2,14 +2,15 @@
#define PCI_OPS_H #define PCI_OPS_H
#include <stdint.h> #include <stdint.h>
struct device; #include <device/device.h>
uint8_t pci_read_config8(device_t dev, unsigned where);
uint16_t pci_read_config16(device_t dev, unsigned where);
uint32_t pci_read_config32(device_t dev, unsigned where);
void pci_write_config8(device_t dev, unsigned where, uint8_t val);
void pci_write_config16(device_t dev, unsigned where, uint16_t val);
void pci_write_config32(device_t dev, unsigned where, uint32_t val);
int pci_read_config_byte(struct device *dev, uint8_t where, uint8_t *val);
int pci_read_config_word(struct device *dev, uint8_t where, uint16_t *val);
int pci_read_config_dword(struct device *dev, uint8_t where, uint32_t *val);
int pci_write_config_byte(struct device *dev, uint8_t where, uint8_t val);
int pci_write_config_word(struct device *dev, uint8_t where, uint16_t val);
int pci_write_config_dword(struct device *dev, uint8_t where, uint32_t val);
void pci_set_method(void); void pci_set_method(void);
#endif /* PCI_OPS_H */ #endif /* PCI_OPS_H */

12
src/southbridge/amd/amd8111/amd8111_ide.c
View File

@ -14,7 +14,7 @@ static void ide_init(struct device *dev)
printk_debug("ide_init\n"); printk_debug("ide_init\n");
pci_read_config_word(dev, 0x40, &word); word = pci_read_config16(dev, 0x40);
/* Ensure prefetch is disabled */ /* Ensure prefetch is disabled */
word &= ~((1 << 15) | (1 << 13)); word &= ~((1 << 15) | (1 << 13));
if (enable_b) { if (enable_b) {
@ -31,10 +31,10 @@ static void ide_init(struct device *dev)
word |= (1<<12); word |= (1<<12);
word |= (1<<14); word |= (1<<14);
pci_write_config_word(dev, 0x40, word); pci_write_config16(dev, 0x40, word);
word = 0x0f; word = 0x0f;
pci_write_config_word(dev, 0x42, word); pci_write_config16(dev, 0x42, word);
/* The AMD768 has a bug where the BM DMA address must be /* The AMD768 has a bug where the BM DMA address must be
* 256 byte aligned while it is only 16 bytes long. * 256 byte aligned while it is only 16 bytes long.
@ -43,11 +43,11 @@ static void ide_init(struct device *dev)
* FIXME: I assume the 8111 does the same thing. We should * FIXME: I assume the 8111 does the same thing. We should
* clarify. stepan@suse.de * clarify. stepan@suse.de
*/ */
pci_write_config_dword(dev, 0x20, 0xf01); pci_write_config32(dev, 0x20, 0xf01);
pci_write_config_dword(dev, 0x48, 0x205e5e5e); pci_write_config32(dev, 0x48, 0x205e5e5e);
word = 0x06a; word = 0x06a;
pci_write_config_word(dev, 0x4c, word); pci_write_config16(dev, 0x4c, word);
} }
static struct device_operations ide_ops = { static struct device_operations ide_ops = {

15
src/southbridge/amd/amd8111/amd8111_lpc.c
View File

@ -1,3 +1,6 @@
/*
* (C) 2003 Linux Networx
*/
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
@ -94,24 +97,24 @@ static void lpc_init(struct device *dev)
#if 0 #if 0
/* IO APIC initialization */ /* IO APIC initialization */
pci_read_config_byte(dev, 0x4B, &byte); byte = pci_read_config8(dev, 0x4B);
byte |= 1; byte |= 1;
pci_write_config_byte(dev, 0x4B, byte); pci_write_config8(dev, 0x4B, byte);
setup_ioapic(); setup_ioapic();
#endif #endif
/* posted memory write enable */ /* posted memory write enable */
pci_read_config_byte(dev, 0x46, &byte); byte = pci_read_config8(dev, 0x46);
pci_write_config_byte(dev, 0x46, byte | (1<<0)); pci_write_config8(dev, 0x46, byte | (1<<0));
/* power after power fail */ /* power after power fail */
pci_read_config_byte(dev, 0x43, &byte); byte = pci_read_config8(dev, 0x43);
if (pwr_on) { if (pwr_on) {
byte &= ~(1<<6); byte &= ~(1<<6);
} else { } else {
byte |= (1<<6); byte |= (1<<6);
} }
pci_write_config_byte(dev, 0x43, byte); pci_write_config8(dev, 0x43, byte);
} }

4
src/southbridge/amd/amd8111/amd8111_usb.c
View File

@ -9,8 +9,8 @@ static void usb_init(struct device *dev)
uint32_t cmd; uint32_t cmd;
printk_debug("USB: Setting up controller.. "); printk_debug("USB: Setting up controller.. ");
pci_read_config_dword(dev, PCI_COMMAND, &cmd); cmd = pci_read_config32(dev, PCI_COMMAND);
pci_write_config_dword(dev, PCI_COMMAND, pci_write_config32(dev, PCI_COMMAND,
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);