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sc7180: Add target specific GPIO pin definitions 

The common gpio driver can be re-used for SC7180,
thus remove the existing gpio driver support and
also clean up the common macro definitions.

Add GPIO pin details specific to SC7180 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.

TEST=Validated on qualcomm sc7180 development board

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Taniya Das 2021-05-20 14:18:53 +05:30 committed by Shelley Chen
parent 2eb3ec7563
commit 7a6b2ef25e
3 changed files with 3 additions and 214 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/qualcomm/sc7180/Makefile.inc
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@ -6,7 +6,7 @@ decompressor-y += mmu.c
decompressor-y += ../common/timer.c decompressor-y += ../common/timer.c
all-y += ../common/timer.c all-y += ../common/timer.c
all-y += spi.c all-y += spi.c
all-y += gpio.c all-y += ../common/gpio.c
all-y += qupv3_i2c.c all-y += qupv3_i2c.c
all-y += qupv3_spi.c all-y += qupv3_spi.c
all-y += clock.c all-y += clock.c

89
src/soc/qualcomm/sc7180/gpio.c
View File

@ -1,89 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <device/mmio.h>
#include <types.h>
#include <gpio.h>
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
uint32_t drive_str, uint32_t enable)
{
uint32_t reg_val;
struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
/* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */
assert(pull <= GPIO_PULL_UP);
reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) |
((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) |
((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) |
((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT);
write32(&regs->cfg, reg_val);
}
void gpio_set(gpio_t gpio, int value)
{
struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT);
}
int gpio_get(gpio_t gpio)
{
struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) &
GPIO_IO_IN_BMSK);
}
void gpio_input_pulldown(gpio_t gpio)
{
gpio_configure(gpio, GPIO_FUNC_GPIO,
GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT_DISABLE);
}
void gpio_input_pullup(gpio_t gpio)
{
gpio_configure(gpio, GPIO_FUNC_GPIO,
GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT_DISABLE);
}
void gpio_input(gpio_t gpio)
{
gpio_configure(gpio, GPIO_FUNC_GPIO,
GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_DISABLE);
}
void gpio_output(gpio_t gpio, int value)
{
gpio_set(gpio, value);
gpio_configure(gpio, GPIO_FUNC_GPIO,
GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE);
}
void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull)
{
struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
gpio_configure(gpio, GPIO_FUNC_GPIO,
pull, GPIO_2MA, GPIO_OUTPUT_DISABLE);
clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT);
clrsetbits32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
<< GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE
<< GPIO_INTR_RAW_STATUS_EN_SHIFT);
}
int gpio_irq_status(gpio_t gpio)
{
struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr;
if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK))
return 0;
write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE);
return 1;
}

126
src/soc/qualcomm/sc7180/include/soc/gpio.h
View File

@ -5,112 +5,10 @@
#include <types.h> #include <types.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <soc/gpio_common.h>
typedef struct {
u32 addr;
} gpio_t;
#define TLMM_TILE_SIZE 0x00400000
#define TLMM_GPIO_OFF_DELTA 0x00001000
#define TLMM_GPIO_TILE_NUM 3
#define TLMM_GPIO_IN_OUT_OFF 0x4
#define TLMM_GPIO_ID_STATUS_OFF 0x10
#define GPIO_FUNC_GPIO 0
/* GPIO INTR CFG MASK */
#define GPIO_INTR_DECT_CTL_MASK 0x3
#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1
/* GPIO INTR CFG SHIFT */
#define GPIO_INTR_DECT_CTL_SHIFT 2
#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4
/* GPIO INTR STATUS MASK */
#define GPIO_INTR_STATUS_MASK 0x1
/* GPIO INTR RAW STATUS */
#define GPIO_INTR_RAW_STATUS_ENABLE 1
#define GPIO_INTR_RAW_STATUS_DISABLE 0
/* GPIO INTR STATUS */
#define GPIO_INTR_STATUS_ENABLE 1
#define GPIO_INTR_STATUS_DISABLE 0
/* GPIO INTR CFG MASK */
#define GPIO_INTR_DECT_CTL_MASK 0x3
#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1
/* GPIO INTR CFG SHIFT */
#define GPIO_INTR_DECT_CTL_SHIFT 2
#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4
/* GPIO INTR STATUS MASK */
#define GPIO_INTR_STATUS_MASK 0x1
/* GPIO INTR RAW STATUS */
#define GPIO_INTR_RAW_STATUS_ENABLE 1
#define GPIO_INTR_RAW_STATUS_DISABLE 0
/* GPIO INTR STATUS */
#define GPIO_INTR_STATUS_ENABLE 1
#define GPIO_INTR_STATUS_DISABLE 0
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
#define GPIO_OUTPUT 1
/* GPIO TLMM: Pullup/Pulldown */
#define GPIO_NO_PULL 0
#define GPIO_PULL_DOWN 1
#define GPIO_KEEPER 2
#define GPIO_PULL_UP 3
/* GPIO TLMM: Drive Strength */
#define GPIO_2MA 0
#define GPIO_4MA 1
#define GPIO_6MA 2
#define GPIO_8MA 3
#define GPIO_10MA 4
#define GPIO_12MA 5
#define GPIO_14MA 6
#define GPIO_16MA 7
/* GPIO TLMM: Status */
#define GPIO_OUTPUT_DISABLE 0
#define GPIO_OUTPUT_ENABLE 1
/* GPIO TLMM: Mask */
#define GPIO_CFG_PULL_BMSK 0x3
#define GPIO_CFG_FUNC_BMSK 0xF
#define GPIO_CFG_DRV_BMSK 0x7
#define GPIO_CFG_OE_BMSK 0x1
/* GPIO TLMM: Shift */
#define GPIO_CFG_PULL_SHFT 0
#define GPIO_CFG_FUNC_SHFT 2
#define GPIO_CFG_DRV_SHFT 6
#define GPIO_CFG_OE_SHFT 9
/* GPIO IO: Mask */
#define GPIO_IO_IN_BMSK 0x1
#define GPIO_IO_OUT_BMSK 0x1
/* GPIO IO: Shift */
#define GPIO_IO_IN_SHFT 0
#define GPIO_IO_OUT_SHFT 1
/* GPIO ID STATUS: Mask */
#define GPIO_ID_STATUS_BMSK 0x1
/* GPIO MAX Valid # */
#define GPIO_NUM_MAX 118
#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR})
#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \
GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + (index * TLMM_GPIO_OFF_DELTA), \
GPIO##index##_FUNC_##func1 = 1, \ GPIO##index##_FUNC_##func1 = 1, \
GPIO##index##_FUNC_##func2 = 2, \ GPIO##index##_FUNC_##func2 = 2, \
GPIO##index##_FUNC_##func3 = 3, \ GPIO##index##_FUNC_##func3 = 3, \
@ -265,24 +163,4 @@ enum {
RES_6, RES_7), RES_6, RES_7),
PIN(118, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(118, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
}; };
enum gpio_irq_type {
IRQ_TYPE_LEVEL = 0,
IRQ_TYPE_RISING_EDGE = 1,
IRQ_TYPE_FALLING_EDGE = 2,
IRQ_TYPE_DUAL_EDGE = 3,
};
struct tlmm_gpio {
uint32_t cfg;
uint32_t in_out;
uint32_t intr_cfg;
uint32_t intr_status;
};
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
uint32_t drive_str, uint32_t enable);
void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull);
int gpio_irq_status(gpio_t gpio);
#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */ #endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */