cpu/intel/car/core2: Prepare for POSTCAR_STAGE support
Split of the model_6ex cache as ram to support POSTCAR_STAGE, which is also needed for future C_ENVIRONMENT_BOOTBLOCK. When using POSTCAR_STAGE the p4-netburst/exit_car.S is using since it is identical. Change-Id: Ibe9f065fdf1d702b73333ea7bb32daca15ba1293 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
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711fb811ac
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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.code32
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_cache_as_ram_setup:
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/* Save the BIST result. */
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movl %eax, %ebp
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself. */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) >> 1), %edi
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xorl %eax, %eax
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xorl %edx, %edx
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clear_mtrrs:
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movw (%esi), %bx
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movzx %bx, %ecx
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wrmsr
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add $2, %esi
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dec %edi
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jnz clear_mtrrs
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post_code(0x22)
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/* Configure the default memory type to uncacheable. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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post_code(0x23)
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/* Set Cache-as-RAM base address. */
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movl $(MTRR_PHYS_BASE(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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post_code(0x24)
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/* Set Cache-as-RAM mask. */
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movl $(MTRR_PHYS_MASK(0)), %ecx
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movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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post_code(0x25)
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/* Enable MTRR. */
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movl $MTRR_DEF_TYPE_MSR, %ecx
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rdmsr
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orl $MTRR_DEF_TYPE_EN, %eax
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wrmsr
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/* Enable L2 cache. */
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movl $0x11e, %ecx
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rdmsr
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orl $(1 << 8), %eax
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wrmsr
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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invd
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movl %eax, %cr0
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/* Clear the cache memory region. This will also fill up the cache. */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
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// movl $0x23322332, %eax
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xorl %eax, %eax
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rep stosl
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post_code(0x26)
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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/* Enable cache for our code in Flash because we do XIP here */
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movl $MTRR_PHYS_BASE(1), %ecx
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xorl %edx, %edx
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/*
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* IMPORTANT: The following calculation _must_ be done at runtime. See
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* https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
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*/
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movl $copy_and_run, %eax
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andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
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orl $MTRR_TYPE_WRPROT, %eax
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wrmsr
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movl $MTRR_PHYS_MASK(1), %ecx
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movl $CPU_PHYSMASK_HI, %edx
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movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
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wrmsr
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post_code(0x28)
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
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movl %eax, %cr0
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/* Setup the stack. */
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movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
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movl %eax, %esp
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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before_romstage:
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post_code(0x29)
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/* Call romstage.c main function. */
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call romstage_main
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/* Should never see this postcode */
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post_code(POST_DEAD_CODE)
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.Lhlt:
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hlt
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jmp .Lhlt
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mtrr_table:
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/* Fixed MTRRs */
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.word 0x250, 0x258, 0x259
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.word 0x268, 0x269, 0x26A
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.word 0x26B, 0x26C, 0x26D
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.word 0x26E, 0x26F
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/* Variable MTRRs */
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.word 0x200, 0x201, 0x202, 0x203
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.word 0x204, 0x205, 0x206, 0x207
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.word 0x208, 0x209, 0x20A, 0x20B
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.word 0x20C, 0x20D, 0x20E, 0x20F
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mtrr_table_end:
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_cache_as_ram_setup_end:
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@ -8,6 +8,11 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
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ifneq ($(CONFIG_POSTCAR_STAGE),y)
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cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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else
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cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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endif
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romstage-y += ../car/romstage.c
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@ -11,5 +11,11 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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ifneq ($(CONFIG_POSTCAR_STAGE),y)
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cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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else
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cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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endif
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romstage-y += ../car/romstage.c
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@ -9,6 +9,11 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
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ifneq ($(CONFIG_POSTCAR_STAGE),y)
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cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
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else
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cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
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postcar-y += ../car/p4-netburst/exit_car.S
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endif
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romstage-y += ../car/romstage.c
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