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amd/stoneyridge: Make UMA memory cacheable 

Use reserved_ram_resource to help ensure the UMA memory is typed
as WB.

BUG=b:65856868
TEST=Inspect MTRRs and compare with UMA memory

Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21606
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2017-09-19 16:26:34 -06:00 committed by Martin Roth
parent bbf91af9a2
commit 7ac2af32f3
1 changed files with 8 additions and 1 deletions
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9
src/soc/amd/stoneyridge/northbridge.c
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@ -484,7 +484,14 @@ void domain_set_resources(device_t dev)
" limitk=%08llx\n", mmio_basek, basek, limitk);
}
add_uma_resource_below_tolm(dev, 7);
/* UMA is not set up yet, but infer the base & size to make cacheable */
uint32_t uma_base = restore_top_of_low_cacheable();
if (uma_base != bsp_topmem()) {
uint32_t uma_size = bsp_topmem() - uma_base;
printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
__func__, uma_size, uma_base);
reserved_ram_resource(dev, 7, uma_base / KiB, uma_size / KiB);
}
for (link = dev->link_list ; link ; link = link->next)
if (link->children)