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Add a kconfig option to allow the user to select a specific physical 

USB port for use as Debug Port (on chipsets which support that).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-09-27 18:03:18 +00:00
parent 5211a7023e
commit 7ac4c26177
8 changed files with 28 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/console/Kconfig
View File

@ -112,6 +112,27 @@ config USBDEBUG
If unsure, say N.
# Note: This option doesn't make sense on Intel ICH southbridges as those
# hardcode the physical USB port to be used as Debug Port to 1. It cannot
# be changed by coreboot.
config USBDEBUG_DEFAULT_PORT
int "Default USB port to use as Debug Port"
default 1
depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX
help
This option selects which physical USB port coreboot will try to
use as EHCI Debug Port first (valid values are: 1-15).
If coreboot doesn't detect an EHCI Debug Port dongle on this port,
it will try all the other ports one after the other. This will take
a few seconds of time though, and thus slow down the booting process.
Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number (1-15) refers to which
actual port on your mainboard (potentially also USB pin headers
on your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.
config CONSOLE_VGA
bool "Use VGA console once initialized"
default n

4
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -40,8 +40,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -196,7 +194,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
sis966_enable_usbdebug(DBGP_DEFAULT);
sis966_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();

4
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -38,8 +38,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -212,7 +210,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();

4
src/mainboard/msi/ms7260/romstage.c
View File

@ -42,8 +42,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -181,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
uart_init();
report_bist_failure(bist); /* Halt upon BIST failure. */
#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();

4
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -33,8 +33,6 @@
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -185,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif

4
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -38,8 +38,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -198,7 +196,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();

4
src/mainboard/tyan/s2912/romstage.c
View File

@ -38,8 +38,6 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -192,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif
console_init();

4
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -33,8 +33,6 @@
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -180,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
#if CONFIG_USBDEBUG
mcp55_enable_usbdebug(DBGP_DEFAULT);
mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
#endif