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mb/siemens/mc_apl5: Set Full Reset Bit into Reset Control Register 

With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78 ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.

Change-Id: Ia8b7f997ca6234add569da751e1070144790e258
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2023-05-09 09:49:13 +02:00 committed by Felix Held
parent 08706a3ad0
commit 7ad8b0987a
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <cf9_reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@ -59,6 +60,11 @@ void variant_mainboard_final(void)
if (parent && parent->device == PCI_DID_TI_XIO2001)
pci_write_config8(parent, 0xd8, 0x3e);
}
/* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1
and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is
then used on the mainboard to generate the right reset timing. */
outb(FULL_RST, RST_CNT);
}
static void finalize_boot(void *unused)