diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index d1ee6f775c..11a0084c70 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -21,16 +21,19 @@
 #define  SPD_DRAM_LPDDR5	0x13
 #define SPD_DENSITY_BANKS	4
 #define SPD_ADDRESSING		5
+#define SPD_SN_LEN		4
 #define DDR3_ORGANIZATION	7
 #define DDR3_BUS_DEV_WIDTH	8
 #define DDR4_ORGANIZATION	12
 #define DDR4_BUS_DEV_WIDTH	13
 #define DDR3_SPD_PART_OFF	128
 #define DDR3_SPD_PART_LEN	18
+#define DDR3_SPD_SN_OFF		122
 #define LPDDR3_SPD_PART_OFF	128
 #define LPDDR3_SPD_PART_LEN	18
 #define DDR4_SPD_PART_OFF	329
 #define DDR4_SPD_PART_LEN	20
+#define DDR4_SPD_SN_OFF		325
 
 struct spd_block {
 	u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
@@ -45,6 +48,13 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index);
 void dump_spd_info(struct spd_block *blk);
 void get_spd_smbus(struct spd_block *blk);
 
+/*
+ * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4.
+ *  return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
+ *  return CB_ERR, if dram_type is not supported or addr is a zero.
+ */
+enum cb_err get_spd_sn(u8 addr, u32 *sn);
+
 /* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
    verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
 int read_ddr3_spd_from_cbfs(u8 *buf, int idx);
diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c
index f7192c85d4..5441b06219 100644
--- a/src/soc/intel/common/block/smbus/smbuslib.c
+++ b/src/soc/intel/common/block/smbus/smbuslib.c
@@ -79,3 +79,51 @@ void get_spd_smbus(struct spd_block *blk)
 
 	update_spd_len(blk);
 }
+
+/*
+ * get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4.
+ *  return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
+ *  return CB_ERR, if dram_type is not supported or addr is a zero.
+ */
+enum cb_err get_spd_sn(u8 addr, u32 *sn)
+{
+	u8 i;
+	u8 dram_type;
+	int smbus_ret;
+
+	/* addr is not a zero. */
+	if (addr == 0x0)
+		return CB_ERR;
+
+	/* If dimm is not present, set sn to 0xff. */
+	smbus_ret = do_smbus_read_byte(SMBUS_IO_BASE, addr, SPD_DRAM_TYPE);
+	if (smbus_ret < 0) {
+		printk(BIOS_INFO, "No memory dimm at address %02X\n", addr);
+		*sn = 0xffffffff;
+		return CB_SUCCESS;
+	}
+
+	dram_type = smbus_ret & 0xff;
+
+	/* Check if module is DDR4, DDR4 spd is 512 byte. */
+	if (dram_type == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+		/* Switch to page 1 */
+		do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_1, 0, 0);
+
+		for (i = 0; i < SPD_SN_LEN; i++)
+			*((u8 *)sn + i) = do_smbus_read_byte(SMBUS_IO_BASE, addr,
+						i + DDR4_SPD_SN_OFF);
+
+		/* Restore to page 0 */
+		do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_0, 0, 0);
+	} else if (dram_type == SPD_DRAM_DDR3) {
+		for (i = 0; i < SPD_SN_LEN; i++)
+			*((u8 *)sn + i) = do_smbus_read_byte(SMBUS_IO_BASE, addr,
+							i + DDR3_SPD_SN_OFF);
+	} else {
+		printk(BIOS_ERR, "Unsupported dram_type\n");
+		return CB_ERR;
+	}
+
+	return CB_SUCCESS;
+}