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mb/google/brya/var/kinox: Update the DPTF parameters and fan table 

Follow the Thermal_paramters_list-0902.xlsx to modify DPTF parameters
and fan table.

1. Modify CRT of TSR0 - TSR3 to 97.
2. Modify TCC offset to 6.
3. Update new fan table.

BUG=b:244657172
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67314
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dtrain Hsu 2022-09-02 16:33:32 +08:00 committed by Martin Roth
parent ed688abe51
commit 7afa1bae2b
1 changed files with 45 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
src/mainboard/google/brya/variants/kinox/overridetree.cb
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@ -69,6 +69,8 @@ chip soc/intel/alderlake
.tdp_pl1_override = 30,
}"
register "tcc_offset" = "6"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
@ -82,68 +84,63 @@ chip soc/intel/alderlake
## Active Policy
register "policies.active" = "{
[0] = {
.target = DPTF_CPU,
.target = DPTF_TEMP_SENSOR_0,
.thresholds = {
TEMP_PCT(80, 97),
TEMP_PCT(65, 93),
TEMP_PCT(58, 86),
TEMP_PCT(50, 80),
TEMP_PCT(45, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 47),
TEMP_PCT(90, 97),
TEMP_PCT(60, 80),
TEMP_PCT(55, 70),
TEMP_PCT(50, 64),
TEMP_PCT(45, 54),
TEMP_PCT(42, 47),
TEMP_PCT(38, 43),
TEMP_PCT(35, 40),
TEMP_PCT(33, 36),
TEMP_PCT(30, 32),
}
},
[1] = {
.target = DPTF_TEMP_SENSOR_0,
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
TEMP_PCT(75, 97),
TEMP_PCT(70, 93),
TEMP_PCT(60, 86),
TEMP_PCT(52, 80),
TEMP_PCT(47, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 47),
TEMP_PCT(90, 97),
TEMP_PCT(60, 80),
TEMP_PCT(55, 70),
TEMP_PCT(50, 64),
TEMP_PCT(45, 54),
TEMP_PCT(42, 47),
TEMP_PCT(38, 43),
TEMP_PCT(35, 40),
TEMP_PCT(33, 36),
TEMP_PCT(30, 32),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_1,
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
TEMP_PCT(75, 97),
TEMP_PCT(70, 93),
TEMP_PCT(60, 86),
TEMP_PCT(52, 80),
TEMP_PCT(47, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 47),
TEMP_PCT(90, 97),
TEMP_PCT(60, 80),
TEMP_PCT(55, 70),
TEMP_PCT(50, 64),
TEMP_PCT(45, 54),
TEMP_PCT(42, 47),
TEMP_PCT(38, 43),
TEMP_PCT(35, 40),
TEMP_PCT(33, 36),
TEMP_PCT(30, 32),
}
},
[3] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
TEMP_PCT(75, 97),
TEMP_PCT(70, 93),
TEMP_PCT(60, 86),
TEMP_PCT(52, 80),
TEMP_PCT(47, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 47),
TEMP_PCT(35, 40),
}
},
[4] = {
.target = DPTF_TEMP_SENSOR_3,
.thresholds = {
TEMP_PCT(75, 97),
TEMP_PCT(70, 93),
TEMP_PCT(60, 86),
TEMP_PCT(52, 80),
TEMP_PCT(47, 64),
TEMP_PCT(43, 52),
TEMP_PCT(40, 47),
TEMP_PCT(90, 97),
TEMP_PCT(60, 80),
TEMP_PCT(55, 70),
TEMP_PCT(50, 64),
TEMP_PCT(45, 54),
TEMP_PCT(42, 47),
TEMP_PCT(38, 43),
TEMP_PCT(35, 40),
TEMP_PCT(33, 36),
TEMP_PCT(30, 32),
}
}
}"
@ -160,10 +157,10 @@ chip soc/intel/alderlake
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 93, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 93, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 93, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 93, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 97, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 97, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 97, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 97, SHUTDOWN),
}"
register "controls.power_limits" = "{