removed unused code, code reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
981faa09e4
commit
7b08c116b9
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@ -31,6 +31,7 @@ static void enumerate(struct chip *chip)
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printk_debug("Enumerating: %s\n", chip->control->name);
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}
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/* update device operation for dynamic root */
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dev_root.ops = &mainboard_operations;
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chip->dev = &dev_root;
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chip->bus = 0;
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@ -6,26 +6,42 @@ uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses ARCH
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uses HAVE_HARD_RESET
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uses HARD_RESET_BUS
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uses HARD_RESET_DEVICE
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uses HARD_RESET_FUNCTION
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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default HARD_RESET_BUS=3
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default HARD_RESET_DEVICE=4
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default HARD_RESET_FUNCTION=0
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#
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#
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###
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### Build the objects we have code for in this directory.
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### Build code to export a programmable irq routing table
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###
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=11
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config chip.h
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register "fixup_scsi" = "1"
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register "fixup_vga" = "1"
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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@ -34,22 +50,43 @@ default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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###
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### Build code for SMP support
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### Only worry about 2 micro processors
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###
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=2
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#
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###
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### Build code to setup a generic IOAPIC
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###
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default CONFIG_IOAPIC=1
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###
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### Clean up the motherboard id strings
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###
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default MAINBOARD_PART_NUMBER="S2885"
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default MAINBOARD_VENDOR="Tyan"
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###
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### Set all of the defaults for an x86 architecture
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###
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arch i386 end
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###
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### Build the objects we have code for in this directory.
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###
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driver mainboard.o
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#dir /drvers/adaptec/7902
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#dir /drivers/si/3114
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#dir /drivers/intel/82551
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driver ti_firewire.o
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#driver ti_firewire.o
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#dir /drivers/vga
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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default HARD_RESET_BUS=3
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default HARD_RESET_DEVICE=4
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default HARD_RESET_FUNCTION=0
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#
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#
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arch i386 end
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#
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###
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@ -72,7 +109,7 @@ else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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#
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@ -149,6 +186,9 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
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### Include the secondary Configuration files
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###
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dir /pc80
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config chip.h
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register "fixup_scsi" = "1"
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register "fixup_vga" = "1"
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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@ -192,7 +232,7 @@ northbridge amd/amdk8 "mc0"
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pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x70 = 1
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irq 0x72 = 12
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pnp 2e.6 off # CIR
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pnp 2e.7 off # GAME_MIDI_GIPO1
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@ -218,11 +258,9 @@ northbridge amd/amdk8 "mc1"
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pci 0:19.3
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end
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#dir /bioscall
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cpu k8 "cpu0"
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register "ldt0" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
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register "ldt2" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
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register "ldt0" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
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register "ldt2" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
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end
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cpu k8 "cpu1"
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@ -1,5 +1,4 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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@ -26,38 +25,37 @@
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static void hard_reset(void)
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{
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set_bios_reset();
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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}
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else {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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}
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if (is_cpu_pre_c0()) {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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} else {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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}
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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udelay(90);
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}
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if (is_cpu_pre_c0()) {
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udelay(800);
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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udelay(90);
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}
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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@ -84,21 +82,21 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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* [3] Route to Link 2
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*/
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uint32_t ret=0x00010101; /* default row entry */
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uint32_t ret = 0x00010101; /* default row entry */
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/* CPU0 LDT1 <-> LDT1 CPU1 */
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static const unsigned int rows_2p[2][2] = {
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{ 0x00050101, 0x00010404 },
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{ 0x00010404, 0x00050101 }
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};
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if(maxnodes>2) {
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if (maxnodes > 2) {
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print_debug("this mainboard is only designed for 2 cpus\r\n");
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maxnodes=2;
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maxnodes = 2;
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}
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if (!(node>=maxnodes || row>=maxnodes)) {
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ret=rows_2p[node][row];
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if (!(node >= maxnodes || row >= maxnodes)) {
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ret = rows_2p[node][row];
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}
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return ret;
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@ -168,68 +166,43 @@ static void main(void)
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int needs_reset;
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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asm volatile ("jmp __cpu_reset");
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}
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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setup_s2885_resource_map();
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needs_reset = setup_coherent_ht_domain();
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#if 0
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
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#else
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needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
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#endif
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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#if 0
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dump_pci_devices();
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#endif
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#if 0
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print_pci_devices();
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#endif
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu[0]);
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#endif
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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#if 0
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dump_pci_devices();
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#endif
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 1));
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#endif
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/* Check all of memory */
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM2);
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print_debug("TOP_MEM2: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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#endif
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/*
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#if 0
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ram_check(0x00000000, msr.lo+(msr.hi<<32));
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#else
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#if TOTAL_CPUS < 2
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// Check 16MB of memory @ 0
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ram_check(0x00000000, 0x00100000);
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#else
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// Check 16MB of memory @ 2GB
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ram_check(0x80000000, 0x80100000);
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#endif
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#endif
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*/
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}
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@ -60,17 +60,17 @@ static void main(void)
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goto fallback_image;
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}
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normal_image:
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asm("jmp __normal_image"
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: /* outputs */
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: "a" (bist) /* inputs */
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: /* clobbers */
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);
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asm volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist) /* inputs */
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: /* clobbers */
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);
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cpu_reset:
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asm("jmp __cpu_reset"
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: /* outputs */
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: "a"(bist) /* inputs */
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: /* clobbers */
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);
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asm volatile ("jmp __cpu_reset"
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: /* outputs */
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: "a"(bist) /* inputs */
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: /* clobbers */
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);
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fallback_image:
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#if HAVE_REGPARM_SUPPORT
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return bist;
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@ -9,164 +9,9 @@
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unsigned long initial_apicid[CONFIG_MAX_CPUS] =
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{
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0,1
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0, 1
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};
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#if 0
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static void fixup_lsi_53c1030(struct device *pdev)
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{
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// uint8_t byte;
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uint16_t word;
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byte = 1;
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pci_write_config8(pdev, 0xff, byte);
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// Set the device id
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// pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030);
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// Set the subsytem vendor id
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// pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);
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word = 0x10f1;
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pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
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// Set the subsytem id
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word = 0x2880;
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pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
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// Disable writes to the device id
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byte = 0;
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pci_write_config8(pdev, 0xff, byte);
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// lsi_scsi_init(pdev);
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}
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#endif
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#if 0
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static void print_pci_regs(struct device *dev)
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{
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uint8_t byte;
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int i;
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for(i=0;i<256;i++) {
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byte = pci_read_config8(dev, i);
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if((i%16)==0) printk_debug("\n%02x:",i);
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printk_debug(" %02x",byte);
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}
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printk_debug("\n");
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// pci_write_config8(dev, 0x4, byte);
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}
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#endif
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#if 0
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static void print_mem(void)
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{
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int i;
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int low_1MB = 0;
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for(i=low_1MB;i<low_1MB+1024*4;i++) {
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if((i%16)==0) printk_debug("\n %08x:",i);
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printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
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}
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for(i=low_1MB;i<low_1MB+1024*4;i++) {
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if((i%16)==0) printk_debug("\n %08x:",i);
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printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
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}
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}
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#endif
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#if 0
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static void amd8111_enable_rom(void)
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{
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uint8_t byte;
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struct device *dev;
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/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
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/* Locate the amd8111 */
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dev = dev_find_device(0x1022, 0x7468, 0);
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/* Set the 4MB enable bit bit */
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byte = pci_read_config8(dev, 0x43);
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byte |= 0x80;
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pci_write_config8(dev, 0x43, byte);
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}
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#endif
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#if 0
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static void onboard_scsi_fixup(void)
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{
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struct device *dev;
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#if 1
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unsigned char i,j,k;
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for(i=0;i<=6;i++) {
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for(j=0;j<=0x1f;j++) {
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for (k=0;k<=6;k++){
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dev = dev_find_slot(i, PCI_DEVFN(j, k));
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if (dev) {
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printk_debug("%02x:%02x:%02x",i,j,k);
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print_pci_regs(dev);
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}
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}
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}
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}
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#endif
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#if 0
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dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
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if(!dev) {
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printk_info("LSI_SCSI_FW_FIXUP: No Device Found!");
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return;
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}
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lsi_scsi_init(dev);
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#endif
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// print_mem();
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// amd8111_enable_rom();
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}
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#endif
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#if 0
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static void vga_fixup(void) {
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// we do this right here because:
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// - all the hardware is working, and some VGA bioses seem to need
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// that
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// - we need page 0 below for linuxbios tables.
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#if CONFIG_REALMODE_IDT == 1
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printk_debug("INSTALL REAL-MODE IDT\n");
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setup_realmode_idt();
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#endif
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#if CONFIG_VGABIOS == 1
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printk_debug("DO THE VGA BIOS\n");
|
||||
do_vgabios(0x0600);
|
||||
post_code(0x93);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static void
|
||||
enable(struct chip *chip, enum chip_pass pass)
|
||||
{
|
||||
|
||||
struct mainboard_tyan_s2885_config *conf =
|
||||
(struct mainboard_tyan_s2885_config *)chip->chip_info;
|
||||
|
||||
switch (pass) {
|
||||
default: break;
|
||||
// case CONF_PASS_PRE_CONSOLE:
|
||||
// case CONF_PASS_PRE_PCI:
|
||||
// case CONF_PASS_POST_PCI:
|
||||
case CONF_PASS_PRE_BOOT:
|
||||
// if (conf->fixup_scsi)
|
||||
// onboard_scsi_fixup();
|
||||
// if (conf->fixup_vga)
|
||||
// vga_fixup();
|
||||
printk_debug("mainboard fixup pass %d done\r\n",
|
||||
pass);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
|
|
@ -180,6 +25,10 @@ static void enumerate(struct chip *chip)
|
|||
{
|
||||
struct chip *child;
|
||||
|
||||
if (chip->control && chip->control->name) {
|
||||
printk_debug("Enumerating: %s\n", chip->control->name);
|
||||
}
|
||||
|
||||
/* update device operation for dynamic root */
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
|
|
@ -188,8 +37,8 @@ static void enumerate(struct chip *chip)
|
|||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_control mainboard_tyan_s2885_control = {
|
||||
.enable = enable,
|
||||
.enumerate = enumerate,
|
||||
.name = "Tyan s2885 mainboard ",
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue