Trivial. re-Indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -776,7 +776,7 @@ static u8 NodePresent_D(u8 Node)
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if (val == dword) /* current nodeID = requested nodeID ? */
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ret = 1;
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finish:
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;
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;
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}
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return ret;
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@ -1040,33 +1040,33 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
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if (byte & 0xF0) {
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val++; /* round up in case fractional extention is non-zero.*/
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}
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}
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if (Trc < val)
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Trc = val;
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}
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if (Trc < val)
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Trc = val;
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/* dev density=rank size/#devs per rank */
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byte = mctRead_SPD(smbaddr, SPD_BANKSZ);
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/* dev density=rank size/#devs per rank */
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byte = mctRead_SPD(smbaddr, SPD_BANKSZ);
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val = ((byte >> 5) | (byte << 3)) & 0xFF;
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val <<= 2;
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val = ((byte >> 5) | (byte << 3)) & 0xFF;
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val <<= 2;
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byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */
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if (byte == 4) {
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val >>= 4;
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} else if (byte == 8) {
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val >>= 3;
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} else if (byte == 16) {
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val >>= 2;
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}
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byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */
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if (byte == 4) {
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val >>= 4;
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} else if (byte == 8) {
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val >>= 3;
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} else if (byte == 16) {
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val >>= 2;
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}
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byte = bsr(val);
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byte = bsr(val);
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if (Trfc[LDIMM] < byte)
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Trfc[LDIMM] = byte;
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if (Trfc[LDIMM] < byte)
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Trfc[LDIMM] = byte;
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byte = mctRead_SPD(smbaddr, SPD_TRAS);
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if (Tras < byte)
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Tras = byte;
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byte = mctRead_SPD(smbaddr, SPD_TRAS);
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if (Tras < byte)
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Tras = byte;
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} /* Dimm Present */
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}
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@ -1129,7 +1129,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
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}
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pDCTstat->Trp = val;
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/*Trrd*/
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/*Trrd*/
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dword = Trrd * 10;
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pDCTstat->DIMMTrrd = dword;
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val = dword / Tk40;
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@ -2183,8 +2183,8 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
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pDCTstat->DimmECCPresent |= 1 << i;
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}
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if (byte & JED_ADRCPAR) {
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/* DIMM is ECC capable */
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pDCTstat->DimmPARPresent |= 1 << i;
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/* DIMM is ECC capable */
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pDCTstat->DimmPARPresent |= 1 << i;
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}
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/* Check if x4 device */
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devwidth = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE;
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@ -2455,8 +2455,8 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
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if (byte != bytex) {
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pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO);
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} else {
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if ( mctGet_NVbits(NV_Unganged) )
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pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
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if ( mctGet_NVbits(NV_Unganged) )
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pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
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if (!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) {
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pDCTstat->GangedMode = 1;
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@ -2872,7 +2872,7 @@ static void Get_Twrwr(struct MCTStatStruc *pMCTstat,
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dword = bsr(pDCTstat->DIMMValid);
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if (dword != val && dword != 0) {
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/*the largest WrDatGrossDlyByte of any DIMM minus the
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WrDatGrossDlyByte of any other DIMM is equal to CGDD */
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WrDatGrossDlyByte of any other DIMM is equal to CGDD */
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val = Get_WrDatGross_Diff(pDCTstat, dct, dev, index_reg);
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}
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if (val == 0)
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@ -3128,7 +3128,7 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
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Largest = byte;
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}
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}
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index += 3;
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index += 3;
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} /* while ++i */
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word = Smallest;
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@ -3265,7 +3265,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
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dev = pDCTstat->dev_map;
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/* Copy dram map from F1x40/44,F1x48/4c,
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to F1x120/124(Node0),F1x120/124(Node1),...*/
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to F1x120/124(Node0),F1x120/124(Node1),...*/
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for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) {
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pDCTstat = pDCTstatA + Node;
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devx = pDCTstat->dev_map;
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@ -3738,7 +3738,7 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
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Set_NB32_index_wait(dev, index_reg, index, val | (1 << DisAutoComp));
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//FIXME: check for Bx Cx CPU
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// if Ax mct_SetDramConfigHi_Samp_D
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// if Ax mct_SetDramConfigHi_Samp_D
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/* errata#177 */
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index = 0x4D014F00; /* F2x[1, 0]9C_x[D0FFFFF:D000000] DRAM Phy Debug Registers */
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@ -2814,7 +2814,7 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
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Largest = byte;
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}
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}
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index += 3;
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index += 3;
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} /* while ++i */
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word = Smallest;
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