mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Wyvern
V.2: Spare USB routed internally to another peripheral and so no plug event hook needed. BUG=b:1603699358,b:157479891 BRANCH=none TEST=none Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -81,6 +81,16 @@ chip soc/intel/cannonlake
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
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# Bitmap for Wake Enable on USB attach/detach
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register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
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USB_PORT_WAKE_ENABLE(2) | \
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USB_PORT_WAKE_ENABLE(3) | \
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USB_PORT_WAKE_ENABLE(6)"
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register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
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USB_PORT_WAKE_ENABLE(2) | \
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USB_PORT_WAKE_ENABLE(3) | \
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USB_PORT_WAKE_ENABLE(5)"
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# Enable eMMC HS400
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# Enable eMMC HS400
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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