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intel/southbridge/bd82x6x: Add option to set SPI VSCC registers 

These are needed for the hardware-sequencing function of the PCH SPI
interface. Values are specific to the flash chip used on a board.

Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11798
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
This commit is contained in:
Nico Huber 2015-10-01 19:00:51 +02:00 committed by Nico Huber
parent f3214d0248
commit 7b2f9f6994
2 changed files with 20 additions and 0 deletions
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3
src/southbridge/intel/bd82x6x/chip.h
View File

@ -96,6 +96,9 @@ struct southbridge_intel_bd82x6x_config {
uint32_t superspeed_capable_ports;
/* Overcurrent Mapping for USB 3.0 Ports */
uint32_t xhci_overcurrent_mapping;
uint32_t spi_uvscc;
uint32_t spi_lvscc;
};
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */

17
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -480,6 +480,21 @@ static void pch_decode_init(struct device *dev)
pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
}
static void pch_spi_init(const struct device *const dev)
{
const config_t *const config = dev->chip_info;
printk(BIOS_DEBUG, "pch_spi_init\n");
if (config->spi_uvscc)
RCBA32(0x3800 + 0xc8) = config->spi_uvscc;
if (config->spi_lvscc)
RCBA32(0x3800 + 0xc4) = config->spi_lvscc;
if (config->spi_uvscc || config->spi_lvscc)
RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */
}
static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: lpc_init\n");
@ -536,6 +551,8 @@ static void lpc_init(struct device *dev)
pch_set_acpi_mode();
pch_fixups(dev);
pch_spi_init(dev);
}
static void pch_lpc_read_resources(device_t dev)