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soc/intel/skl: Drop FSP_CAR remnants 

FSP-T support was abandoned long ago for Skylake. With FSP1.1 support
also dropped now, it's more visible that this code is unused.

Change-Id: I83a9130ef403b498e2beea01749c178e547b0f08
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37251
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2019-11-26 18:30:40 +01:00 committed by Patrick Georgi
parent 693e04f5c6
commit 7b3e8730ee
3 changed files with 0 additions and 45 deletions
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1
src/soc/intel/skylake/Kconfig
View File

@ -31,7 +31,6 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_INTEL_COMMON_HYPERTHREADING
select FSP_M_XIP
select FSP_T_XIP if FSP_CAR
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE

1
src/soc/intel/skylake/Makefile.inc
View File

@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-$(CONFIG_FSP_CAR) += fspcar.c
bootblock-y += bootblock/cpu.c
bootblock-y += i2c.c
bootblock-y += bootblock/pch.c

43
src/soc/intel/skylake/fspcar.c
View File

@ -1,43 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <FsptUpd.h>
const FSPT_UPD temp_ram_init_params = {
.FspUpdHeader = {
.Signature = 0x545F4450554C424B, /* 'KBLUPD_T' */
.Revision = 1,
.Reserved = {0},
},
.FsptCoreUpd = {
/*
* It is a requirement for firmware to have Firmware Interface Table
* (FIT), which contains pointers to each microcode update.
* The microcode update is loaded for all logical processors before
* cpu reset vector.
*
* All SoC since Gen-4 has above mechanism in place to load microcode
* even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to
* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
*/
.MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
},
};