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sb/intel: Use common RCBA MACROs 

This commit follows up on commit 2e464cf3 with Change-Id
I61fb3b01ff15ba2da2ee938addfa630c282c9870.

Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Peter Lemenkov 2018-10-23 11:12:46 +02:00 committed by Patrick Georgi
parent aa6d388597
commit 7b42811fa5
11 changed files with 16 additions and 58 deletions
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2
src/mainboard/emulation/qemu-q35/bootblock.c
View File

@ -59,7 +59,7 @@ static void bootblock_southbridge_init(void)
enable_spi_prefetch();
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,
(uintptr_t)DEFAULT_RCBA | 1);
}

3
src/southbridge/intel/bd82x6x/pch.h
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@ -255,9 +255,6 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define PMBASE 0x40
/* Root Complex Register Block */
#define RCBA 0xf0
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */

14
src/southbridge/intel/common/rcba.h
View File

@ -18,12 +18,12 @@
#define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
/* Root Complex Register Block */
#define RCBA 0xf0
#define RCBA_ENABLE 0x01
#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
@ -36,6 +36,10 @@
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */

22
src/southbridge/intel/fsp_rangeley/soc.h
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@ -41,11 +41,8 @@
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_IBASE 0xfed08000
#define DEFAULT_PBASE 0xfed03000
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#include <southbridge/intel/common/rcba.h>
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
@ -171,21 +168,6 @@ void rangeley_sb_early_initialization(void);
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
/* Root Complex Register Block */
#define RCBA 0xf0
#define RCBA_ENABLE 0x01
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
/* Root Port configuration space hide */
#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
/* Get the function number assigned to a Root Port */

3
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -184,9 +184,6 @@ int southbridge_detect_s3_resume(void);
#define PMBASE 0x40
/* Root Complex Register Block */
#define RCBA 0xf0
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */

2
src/southbridge/intel/i82801ix/early_init.c
View File

@ -22,7 +22,7 @@ void i82801ix_early_init(void)
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
/* Set up RCBA. */
pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
/* Set up PMBASE. */
pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);

1
src/southbridge/intel/i82801ix/i82801ix.h
View File

@ -111,7 +111,6 @@
#define D31F0_CxSTATE_CNF 0xa9
#define D31F0_C4TIMING_CNT 0xaa
#define D31F0_GPIO_ROUT 0xb8
#define D31F0_RCBA 0xf0
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)

2
src/southbridge/intel/i82801jx/bootblock.c
View File

@ -34,6 +34,6 @@ static void bootblock_southbridge_init(void)
enable_spi_prefetch();
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,
(uintptr_t)DEFAULT_RCBA | 1);
}

1
src/southbridge/intel/i82801jx/i82801jx.h
View File

@ -114,7 +114,6 @@
#define D31F0_CxSTATE_CNF 0xa9
#define D31F0_C4TIMING_CNT 0xaa
#define D31F0_GPIO_ROUT 0xb8
#define D31F0_RCBA 0xf0
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)

3
src/southbridge/intel/ibexpeak/pch.h
View File

@ -227,9 +227,6 @@ void southbridge_configure_default_intmap(void);
#define PMBASE 0x40
/* Root Complex Register Block */
#define RCBA 0xf0
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */

21
src/southbridge/intel/lynxpoint/pch.h
View File

@ -83,11 +83,8 @@
#endif
#define HPET_ADDR 0xfed00000
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
#include <southbridge/intel/common/rcba.h>
#ifndef __ACPI__
@ -477,20 +474,6 @@ void mainboard_config_superio(void);
#define PMBASE 0x40
/* Root Complex Register Block */
#define RCBA 0xf0
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
#define VCH 0x0000 /* 32bit */
#define VCAP1 0x0004 /* 32bit */
#define VCAP2 0x0008 /* 32bit */