From 7b4643f5fa170d49217ace787bd00fba0b6c1acc Mon Sep 17 00:00:00 2001
From: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Date: Tue, 21 Jun 2022 09:43:20 -0700
Subject: [PATCH] soc/intel/alderlake: Remove menu option for
 MAX_PCIE_CLOCK_SRC

MAX_PCIE_CLOCK_SRC is not an user-configurable option.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/alderlake/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 58656df8f7..3177a45902 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -242,7 +242,6 @@ config MAX_ROOT_PORTS
 	default MAX_PCH_ROOT_PORTS
 
 config MAX_PCIE_CLOCK_SRC
-	prompt "Number of Source Clock supported from SOC"
 	int
 	default 6 if SOC_INTEL_ALDERLAKE_PCH_M
 	default 5 if SOC_INTEL_ALDERLAKE_PCH_N