cpu/intel: Indent with tabs

Fix the following error and warning detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
WARNING: please, no space before tabs

TEST=Build and run on Galileo Gen2

Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/cpu/intel/car/romstage.c

@@ -26,8 +26,8 @@ void * asmlinkage romstage_main(unsigned long bist)
 	const int num_guards = 4;
 	const u32 stack_guard = 0xdeadbeef;
 	u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
-	                           CONFIG_DCACHE_RAM_SIZE -
-	                           DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+				   CONFIG_DCACHE_RAM_SIZE -
+				   DCACHE_RAM_ROMSTAGE_STACK_SIZE);
 
 	for (i = 0; i < num_guards; i++)
 		stack_base[i] = stack_guard;

src/cpu/intel/fsp_model_206ax/model_206ax.h

@@ -30,7 +30,7 @@
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define IA32_MISC_ENABLE		0x1a0
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_PERF_CTL 			0x199
+#define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
@@ -38,7 +38,7 @@
 #define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
-#define IA32_MC0_STATUS 		0x401
+#define IA32_MC0_STATUS			0x401
 
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce

src/cpu/intel/fsp_model_206ax/model_206ax_init.c

@@ -177,7 +177,7 @@ static void configure_misc(void)
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	  /* Fast String enable */
-	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 

src/cpu/intel/fsp_model_406dx/bootblock.c

@@ -61,7 +61,7 @@ static void enable_rom_caching(void)
 
 	disable_cache();
 	set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1,
-	             CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
+		     CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
 	enable_cache();
 
 	/* Enable Variable MTRRs */

src/cpu/intel/fsp_model_406dx/model_406dx.h

@@ -31,7 +31,7 @@
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define IA32_MISC_ENABLE		0x1a0
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_PERF_CTL 			0x199
+#define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
@@ -39,7 +39,7 @@
 #define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
-#define IA32_MC0_STATUS 		0x401
+#define IA32_MC0_STATUS			0x401
 
 #define MSR_NO_EVICT_MODE		0x2e0
 #define MSR_PIC_MSG_CONTROL		0x2e

src/cpu/intel/haswell/haswell.h

@@ -45,7 +45,7 @@
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define IA32_MISC_ENABLE		0x1a0
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_PERF_CTL 			0x199
+#define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
@@ -53,7 +53,7 @@
 #define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
-#define IA32_MC0_STATUS 		0x401
+#define IA32_MC0_STATUS			0x401
 
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce

src/cpu/intel/haswell/haswell_init.c

@@ -50,7 +50,7 @@
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \
 	C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
-	                              (IRTL_1024_NS >> 10))
+				      (IRTL_1024_NS >> 10))
 
 /*
  * List of supported C-states in this processor. Only the ULT parts support C8,
@@ -361,7 +361,7 @@ static void configure_pch_power_sharing(void)
 	pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
 
 	printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
-               pch_power, pch_power_ext);
+		pch_power, pch_power_ext);
 
 	pmsync = RCBA32(PMSYNC_CONFIG);
 	pmsync2 = RCBA32(PMSYNC_CONFIG2);
@@ -532,19 +532,19 @@ static void configure_c_states(void)
 		/* C-state Interrupt Response Latency Control 3 - package C8 */
 		msr.hi = 0;
 		msr.lo = IRTL_VALID | IRTL_1024_NS |
-		         C_STATE_LATENCY_CONTROL_3_LIMIT;
+			 C_STATE_LATENCY_CONTROL_3_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 
 		/* C-state Interrupt Response Latency Control 4 - package C9 */
 		msr.hi = 0;
 		msr.lo = IRTL_VALID | IRTL_1024_NS |
-		         C_STATE_LATENCY_CONTROL_4_LIMIT;
+			 C_STATE_LATENCY_CONTROL_4_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 
 		/* C-state Interrupt Response Latency Control 5 - package C10 */
 		msr.hi = 0;
 		msr.lo = IRTL_VALID | IRTL_1024_NS |
-		         C_STATE_LATENCY_CONTROL_5_LIMIT;
+			 C_STATE_LATENCY_CONTROL_5_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 	}
 }
@@ -577,7 +577,7 @@ static void configure_misc(void)
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	  /* Fast String enable */
-	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 

src/cpu/intel/haswell/romstage.c

@@ -147,8 +147,8 @@ void * asmlinkage romstage_main(unsigned long bist)
 	const int num_guards = 4;
 	const u32 stack_guard = 0xdeadbeef;
 	u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
-	                           CONFIG_DCACHE_RAM_SIZE -
-	                           CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+				   CONFIG_DCACHE_RAM_SIZE -
+				   CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
 
 	printk(BIOS_DEBUG, "Setting up stack guards.\n");
 	for (i = 0; i < num_guards; i++)

src/cpu/intel/haswell/smmrelocate.c

@@ -221,7 +221,7 @@ static u32 northbridge_get_base_reg(struct device *dev, int reg)
 }
 
 static void fill_in_relocation_params(struct device *dev,
-                                      struct smm_relocation_params *params)
+				      struct smm_relocation_params *params)
 {
 	u32 tseg_size;
 	u32 tsegmb;
@@ -273,7 +273,7 @@ static void fill_in_relocation_params(struct device *dev,
 	params->uncore_emrr_base.lo = emrr_base;
 	params->uncore_emrr_base.hi = 0;
 	params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
-	                              MTRR_PHYS_MASK_VALID;
+				      MTRR_PHYS_MASK_VALID;
 	params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
 }
 
@@ -297,7 +297,9 @@ static void setup_ied_area(struct smm_relocation_params *params)
 
 	/* According to the BWG MP init section 2MiB of memory at IEDBASE +
 	 * 2MiB should be zeroed as well. However, I suspect what is intended
-	 * is to clear the memory covered by EMRR. TODO(adurbin): figure out if 	 * this is really required. */
+	 * is to clear the memory covered by EMRR. TODO(adurbin): figure out if
+	 * this is really required.
+	 */
 	//memset(ied_base + (2 << 20), 0, (2 << 20));
 }
 

src/cpu/intel/model_106cx/model_106cx_init.c

@@ -59,7 +59,7 @@ static void configure_misc(void)
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.lo |= (1 << 3); 	/* TM1 enable */
+	msr.lo |= (1 << 3);	/* TM1 enable */
 	msr.lo |= (1 << 13);	/* TM2 enable */
 	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
 

src/cpu/intel/model_2065x/model_2065x.h

@@ -32,7 +32,7 @@
 #define MSR_TEMPERATURE_TARGET		0x1a2
 #define IA32_FERR_CAPABILITY		0x1f1
 #define   FERR_ENABLE			(1 << 0)
-#define IA32_PERF_CTL 			0x199
+#define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
@@ -40,7 +40,7 @@
 #define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
-#define IA32_MC0_STATUS 		0x401
+#define IA32_MC0_STATUS			0x401
 
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -176,7 +176,7 @@ static void configure_misc(void)
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	  /* Fast String enable */
-	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 

src/cpu/intel/model_206ax/model_206ax.h

@@ -30,7 +30,7 @@
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define IA32_MISC_ENABLE		0x1a0
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_PERF_CTL 			0x199
+#define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
@@ -38,7 +38,7 @@
 #define  ENERGY_POLICY_POWERSAVE	15
 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
 #define MSR_LT_LOCK_MEMORY		0x2e7
-#define IA32_MC0_STATUS 		0x401
+#define IA32_MC0_STATUS			0x401
 
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -336,7 +336,7 @@ static void configure_misc(void)
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	  /* Fast String enable */
-	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 

src/cpu/intel/model_6ex/model_6ex_init.c

@@ -62,7 +62,7 @@ static void configure_misc(void)
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.lo |= (1 << 3); 	/* TM1 enable */
+	msr.lo |= (1 << 3);	/* TM1 enable */
 	msr.lo |= (1 << 13);	/* TM2 enable */
 	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
 

src/cpu/intel/model_6fx/model_6fx_init.c

@@ -65,7 +65,7 @@ static void configure_misc(void)
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
-	msr.lo |= (1 << 3); 	/* TM1 enable */
+	msr.lo |= (1 << 3);	/* TM1 enable */
 	msr.lo |= (1 << 13);	/* TM2 enable */
 	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
 

src/cpu/intel/slot_1/l2_cache.c

@@ -692,7 +692,7 @@ int p6_configure_l2_cache(void)
 	if (v >= 0 && (v & 0x20)) {
 		bblctl3 = rdmsr(BBL_CR_CTL3);
 		bblctl3.lo |= (BBLCR3_L2_ADDR_PARITY_ENABLE |
-		               BBLCR3_L2_CRTN_PARITY_ENABLE);
+			       BBLCR3_L2_CRTN_PARITY_ENABLE);
 		wrmsr(BBL_CR_CTL3, bblctl3);
 	}
 

src/cpu/intel/smm/gen1/smmrelocate.c

@@ -92,13 +92,13 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
 	 * Since one thread runs at a time during the relocation the save state
 	 * is the same for all cpus. */
 	save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE -
-                              runtime->save_state_size);
+			      runtime->save_state_size);
 
 	/* The relocated handler runs with all CPUs concurrently. Therefore
 	 * stagger the entry points adjusting SMBASE downwards by save state
 	 * size * CPU num. */
 	save_state->smbase = relo_params->smram_base -
-	                     cpu * runtime->save_state_size;
+			     cpu * runtime->save_state_size;
 	save_state->iedbase = relo_params->ied_base;
 
 	printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n",
@@ -138,7 +138,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 }
 
 static int install_relocation_handler(int *apic_id_map, int num_cpus,
-                                      struct smm_relocation_params *relo_params)
+				      struct smm_relocation_params *relo_params)
 {
 	/* The default SMM entry happens serially at the default location.
 	 * Therefore, there is only 1 concurrent save state area. Set the
@@ -183,7 +183,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 }
 
 static int install_permanent_handler(int *apic_id_map, int num_cpus,
-                                     struct smm_relocation_params *relo_params)
+				     struct smm_relocation_params *relo_params)
 {
 	/* There are num_cpus concurrent stacks and num_cpus concurrent save
 	 * state areas. Lastly, set the stack size to the save state size. */