Get rid of early_serial, it is now a generic function in early_init.
Add some more enables to the s1850. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
869bbc4616
commit
7b6a0a84be
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@ -13,7 +13,7 @@
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#include "lib/ramtest.c"
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#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
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#include "northbridge/intel/e7520/raminit.h"
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#include "superio/nsc/pc8374/pc8374_early_serial.c"
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#include "superio/nsc/pc8374/pc8374_early_init.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "debug.c"
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@ -65,6 +65,25 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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/* fake it out for this board */
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switch(device) {
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case 0x52:
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case 0x53:
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print_debug("FAKE");
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device = 0x50;
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break;
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case 0x50:
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case 0x51:
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case 0x54:
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case 0x55:
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case 0x56:
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case 0x57:
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print_debug("57");
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device = 0x57;
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break;
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default:
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die("BAD DEV IN spd_read_byte");
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}
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return smbus_read_byte(device, address);
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}
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@ -191,11 +210,22 @@ static void main(unsigned long bist)
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.f1 = PCI_DEV(0, 0x00, 1),
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.f2 = PCI_DEV(0, 0x00, 2),
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.f3 = PCI_DEV(0, 0x00, 3),
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.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
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.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
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.channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
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.channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
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}
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};
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/* superio setup */
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/* observed from serialice */
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static const u8 earlyinit[] = {
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0x21, 0x11, 0x11,
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0x22, 1, 1,
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0x23, 05, 05,
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0x24, 0x81, 0x81,
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0x26, 0, 0,
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0,
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};
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/* using SerialICE, we've seen this basic reset sequence on the dell.
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* we don't understand it as it uses undocumented registers, but
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* we're going to clone it.
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@ -261,10 +291,10 @@ static void main(unsigned long bist)
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pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
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/* ?? */
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l = pci_read_config32(PCI_DEV(0, 0, 8), 0xc0);
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l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
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do_reset = l & 0x8000000;
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l |= 0x8000000;
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pci_write_config32(PCI_DEV(0, 0, 2), 0xc0, l);
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pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
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if (! do_reset) {
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outb(2, 0xcf9);
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@ -279,11 +309,26 @@ static void main(unsigned long bist)
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}
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/* Setup the console */
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mainboard_set_ich5();
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bmc_foad();
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pc8374_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
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//bmc_foad();
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pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
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uart_init();
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console_init();
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/* stuff we seem to need */
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pc8374_enable_dev(PC8374_KBCK, 0);
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/* GPIOs */
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pc8374_enable_dev(PC8374_GPIO, 0xc20);
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/* keep this in mind.
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SerialICE-hlp: outb 002e <= 23
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SerialICE-hlp: inb 002f => 05
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SerialICE-hlp: outb 002f <= 05
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SerialICE-hlp: outb 002e <= 24
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SerialICE-hlp: inb 002f => c1
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SerialICE-hlp: outb 002f <= c1
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*/
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/* Halt if there was a built in self test failure */
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// report_bist_failure(bist);
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@ -306,7 +351,7 @@ static void main(unsigned long bist)
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#if 1
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enable_smbus();
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#endif
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#if 1
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#if 0
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// dump_spd_registers(&cpu[0]);
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int i;
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for(i = 0; i < 1; i++) {
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@ -0,0 +1,37 @@
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#include <arch/romcc_io.h>
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#include "pc8374.h"
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/* things that Must Be Done to get this chip working */
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/* Straight from the data book */
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static void pc8374_enable(unsigned iobase, u8 *init)
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{
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u8 val, count;
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outb(0x29, iobase);
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val = inb(iobase+1);
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val |= 0x91;
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outb(val, iobase+1);
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for(count = 0; count < 255; count++)
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if (inb(iobase+1) == 0x91)
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break;
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for(;*init; init++) {
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outb(*init, iobase);
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val = inb(iobase+1);
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init++;
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val &= *init;
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init++;
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val |= *init;
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outb(val, iobase+1);
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}
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}
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static void pc8374_enable_dev(device_t dev, unsigned iobase)
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{
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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if (iobase)
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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}
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@ -1,11 +0,0 @@
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#include <arch/romcc_io.h>
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#include "pc8374.h"
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static void pc8374_enable_serial(device_t dev, unsigned iobase)
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{
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 1);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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}
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