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vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger Lake

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Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform
version 2457.

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Srinidhi N Kaushik 2020-03-06 14:45:51 -08:00 committed by Patrick Georgi
parent b3bfb2a1a7
commit 7b6a82dc1a
1 changed files with 16 additions and 5 deletions
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21
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
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@ -635,7 +635,18 @@ typedef struct {
/** Offset 0x091A - Reserved
**/
UINT8 Reserved33[438];
UINT8 Reserved33[3];
/** Offset 0x091D - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
Default is 0: Disabled
0: Disabled, 1: Dynamic Configuration
**/
UINT8 HybridStorageMode;
/** Offset 0x091E - Reserved
**/
UINT8 Reserved34[434];
/** Offset 0x0AD0 - RpPtmBytes
**/
@ -643,7 +654,7 @@ typedef struct {
/** Offset 0x0AD4 - Reserved
**/
UINT8 Reserved34[101];
UINT8 Reserved35[101];
/** Offset 0x0B39 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
@ -661,7 +672,7 @@ typedef struct {
/** Offset 0x0B3A - Reserved
**/
UINT8 Reserved35[264];
UINT8 Reserved36[264];
/** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
@ -675,7 +686,7 @@ typedef struct {
/** Offset 0x0CA2 - Reserved
**/
UINT8 Reserved36[269];
UINT8 Reserved37[269];
/** Offset 0x0DAF - LpmStateEnableMask
**/
@ -683,7 +694,7 @@ typedef struct {
/** Offset 0x0DB0 - Reserved
**/
UINT8 Reserved37[80];
UINT8 Reserved38[80];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration