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Simplify a few code chunks, fix whitespace and indentation. 

Also, remove some less useful comments, some dead code / unused functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-21 22:47:22 +00:00
parent 57b2ff886e
commit 7b997053eb
106 changed files with 462 additions and 1343 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/amd/db800/romstage.c
View File

@ -54,11 +54,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
void main(unsigned long bist)
{
post_code(0x01);
@ -76,7 +71,6 @@ void main(unsigned long bist)
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
uart_init();
console_init();

20
src/mainboard/amd/dbm690t/romstage.c
View File

@ -47,17 +47,9 @@
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@ -88,14 +80,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs690_dev8();
sb600_lpc_init();
@ -135,8 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@ -148,7 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}

20
src/mainboard/amd/mahogany/romstage.c
View File

@ -47,17 +47,9 @@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@ -88,14 +80,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs780_dev8();
sb700_lpc_init();
@ -134,8 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@ -147,7 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}

13
src/mainboard/amd/mahogany_fam10/romstage.c
View File

@ -53,15 +53,11 @@ static int smbus_read_byte(u32 device, u32 address);
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@ -78,11 +74,9 @@ static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -91,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}

6
src/mainboard/amd/norwich/romstage.c
View File

@ -51,11 +51,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
void main(unsigned long bist)
{
post_code(0x01);
@ -77,7 +72,6 @@ void main(unsigned long bist)
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
mb_gpio_init();
uart_init();
console_init();

20
src/mainboard/amd/pistachio/romstage.c
View File

@ -42,17 +42,9 @@
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@ -85,14 +77,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sb600_lpc_port80();
/* sb600_pci_port80(); */
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs690_dev8();
sb600_lpc_init();
@ -138,8 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@ -151,7 +140,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}

27
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -33,13 +33,11 @@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@ -54,6 +52,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
#if 0
static inline void change_i2c_mux(unsigned device)
{
@ -80,7 +79,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -117,7 +116,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset;
unsigned bsp_apicid = 0;
#if CONFIG_SET_FIDVID
@ -127,18 +125,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the rom access for 4M */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -188,20 +180,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6) {
{
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
@ -209,13 +198,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
} else {
print_debug("Changing FIDVID not supported\n");
}
#endif
#if 1

11
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
View File

@ -55,8 +55,8 @@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
@ -77,9 +77,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@ -190,8 +188,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {

21
src/mainboard/amd/tilapia_fam10/romstage.c
View File

@ -52,15 +52,11 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@ -78,11 +74,9 @@ static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -91,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}
@ -157,13 +150,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
#endif
post_code(0x38);
@ -171,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
#if CONFIG_SET_FIDVID
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@ -192,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
#endif
rs780_htinit();

32
src/mainboard/arima/hdama/romstage.c
View File

@ -32,14 +32,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@ -47,16 +46,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -85,22 +81,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

8
src/mainboard/artecgroup/dbe61/romstage.c
View File

@ -66,11 +66,6 @@ static int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
void main(unsigned long bist)
{
post_code(0x01);
@ -96,7 +91,6 @@ void main(unsigned long bist)
msr.lo |= 0x7 << 20;
wrmsr(MDD_LEG_IO, msr);
mb_gpio_init();
uart_init();
console_init();
@ -109,7 +103,7 @@ void main(unsigned long bist)
sdram_initialize(1, memctrl);
/* Dump memory configuratation */
/* Dump memory configuration. */
#if 0
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");

9
src/mainboard/asi/mb_5blmp/romstage.c
View File

@ -35,20 +35,11 @@
static void main(unsigned long bist)
{
/* Initialize the serial console. */
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();
/* Check whether RAM works. */
/* ram_check(0x00000000, 0x4000); */
}

20
src/mainboard/asrock/939a785gmh/romstage.c
View File

@ -52,17 +52,9 @@
#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@ -140,14 +132,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs780_dev8();
sb700_lpc_init();
@ -187,8 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@ -200,7 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}

13
src/mainboard/asus/a8n_e/romstage.c
View File

@ -50,15 +50,8 @@
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
static void memreset(int controllers, const struct mem_controller *ctrl)
{
/* Nothing to do. */
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* Nothing to do. */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -108,7 +101,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
@ -138,7 +130,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();

9
src/mainboard/asus/a8v-e_deluxe/romstage.c
View File

@ -52,19 +52,14 @@ unsigned int get_sbdn(unsigned bus);
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
#include <reset.h>
void soft_reset(void)
{

9
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -52,19 +52,14 @@ unsigned int get_sbdn(unsigned bus);
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
#include <reset.h>
void soft_reset(void)
{

9
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -54,19 +54,14 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"

9
src/mainboard/asus/m2v/romstage.c
View File

@ -56,19 +56,14 @@ unsigned int get_sbdn(unsigned bus);
#define IT8712F_GPIO_BASE 0x0a20
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"

15
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -52,15 +52,11 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@ -78,11 +74,9 @@ static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -91,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}
@ -108,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb700_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */
it8712f_kill_watchdog();
uart_init();
#if CONFIG_USBDEBUG

9
src/mainboard/bcom/winnet100/romstage.c
View File

@ -35,20 +35,11 @@
static void main(unsigned long bist)
{
/* Initialize the serial console. */
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();
/* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}

10
src/mainboard/bcom/winnetp680/romstage.c
View File

@ -47,7 +47,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@ -85,26 +86,19 @@ void main(unsigned long bist)
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
print_spew("In romstage.c:main()\n");
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
print_spew("Leaving romstage.c:main()\n");
}

33
src/mainboard/broadcom/blast/romstage.c
View File

@ -26,13 +26,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset_setup(void) { }
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@ -60,7 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -80,36 +75,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
// post_code(0x33);
uart_init();
// post_code(0x34);
console_init();
/* Halt if there was a built in self test failure */
@ -166,9 +148,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif

13
src/mainboard/dell/s1850/romstage.c
View File

@ -67,6 +67,7 @@ static inline void waitobf(void)
while((inb(ipmicsr) & (1<<OBF)) == 0)
;
}
/* quite possibly the stupidest interface ever designed. */
static inline void first_cmd_byte(unsigned char byte)
{
@ -154,12 +155,6 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
/*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
/* the wiring on this part is really messed up */
/* this is my best guess so far */
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
@ -260,10 +255,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Setup the console */
mainboard_set_ich5();
//bmc_foad();
@ -311,9 +305,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
for(i = 0; i < 1; i++)
dump_spd_registers();
}
#endif
#if 1
show_dram_slots();

3
src/mainboard/digitallogic/adl855pc/romstage.c
View File

@ -55,13 +55,12 @@ void main(unsigned long bist)
print_pci_devices();
#endif
if(!bios_reset_detected()) {
if (!bios_reset_detected()) {
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}

5
src/mainboard/digitallogic/msm586seg/romstage.c
View File

@ -42,10 +42,7 @@ struct mem_controller {
int i;
};
static inline int spd_read_byte(unsigned device, unsigned address)
{
// return smbus_read_byte(device, address);
}
static int spd_read_byte(unsigned device, unsigned address) { }
static inline void dumpmem(void){
int i, j;

6
src/mainboard/digitallogic/msm800sev/romstage.c
View File

@ -35,11 +35,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup */
}
void main(unsigned long bist)
{
post_code(0x01);
@ -59,7 +54,6 @@ void main(unsigned long bist)
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
uart_init();
console_init();

25
src/mainboard/eaglelion/5bcm/romstage.c
View File

@ -19,32 +19,7 @@ static void main(unsigned long bist)
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
/* Check all of memory */
#if 0
ram_check(0x00000000, msr.lo);
#endif
#if 0
static const struct {
unsigned long lo, hi;
} check_addrs[] = {
/* Check 16MB of memory @ 0*/
{ 0x00000000, 0x01000000 },
#if TOTAL_CPUS > 1
/* Check 16MB of memory @ 2GB */
{ 0x80000000, 0x81000000 },
#endif
};
int i;
for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
ram_check(check_addrs[i].lo, check_addrs[i].hi);
}
#endif
}

3
src/mainboard/emulation/qemu-x86/romstage.c
View File

@ -13,7 +13,7 @@
static void main(void)
{
/* init_timer();*/
/* init_timer(); */
post_code(0x05);
uart_init();
@ -22,4 +22,3 @@ static void main(void)
//print_pci_devices();
//dump_pci_devices();
}

3
src/mainboard/getac/p470/romstage.c
View File

@ -277,9 +277,8 @@ void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
if (bist == 0) {
if (bist == 0)
enable_lapic();
}
#if 0
/* Force PCIRST# */

24
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -56,14 +56,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -129,25 +123,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the sis966 */
sis966_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x23, 0);
@ -194,21 +182,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif

27
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -121,7 +115,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
uint8_t tmp = 0;
@ -129,18 +122,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
@ -153,9 +141,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
/* We can get away with not resetting the logical device because
* it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
*/
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
@ -200,21 +185,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif

20
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -48,15 +48,11 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@ -76,8 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -86,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}
@ -153,13 +147,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
#endif
post_code(0x38);
@ -167,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
#if CONFIG_SET_FIDVID
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@ -188,7 +182,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
#endif
rs780_htinit();

20
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -52,15 +52,11 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@ -80,8 +76,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -90,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}
@ -155,13 +149,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
#endif
post_code(0x38);
@ -169,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
#if CONFIG_SET_FIDVID
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@ -190,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
#endif
rs780_htinit();

28
src/mainboard/hp/dl145_g1/romstage.c
View File

@ -27,13 +27,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@ -41,8 +41,8 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
@ -108,26 +108,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

13
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -59,9 +59,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@ -133,7 +131,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// first node
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// second node
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
@ -141,24 +138,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

12
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -100,9 +100,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -111,19 +109,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
/* Setup the rom access for 4M */
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
post_code(0x30);
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

3
src/mainboard/ibase/mb899/romstage.c
View File

@ -239,9 +239,8 @@ void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
if (bist == 0) {
if (bist == 0)
enable_lapic();
}
ich7_enable_lpc();
early_superio_config_w83627ehg();

26
src/mainboard/ibm/e325/romstage.c
View File

@ -29,13 +29,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@ -43,16 +43,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -99,15 +96,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
init_cpus(cpu_init_detectedx);
}
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

26
src/mainboard/ibm/e326/romstage.c
View File

@ -29,13 +29,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@ -43,16 +43,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
/* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -99,15 +96,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
init_cpus(cpu_init_detectedx);
}
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

7
src/mainboard/iei/juki-511p/romstage.c
View File

@ -36,12 +36,9 @@
static void main(unsigned long bist)
{
/* Initialize the serial console. */
w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
/* Disable Watchdog Timer. */
@ -49,10 +46,6 @@ static void main(unsigned long bist)
inb(0x843);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();
/* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}

18
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -25,9 +25,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
/* UART address and device number */
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@ -55,15 +52,13 @@ static int smbus_read_byte(u32 device, u32 address);
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@ -81,11 +76,9 @@ static int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -94,7 +87,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}

8
src/mainboard/iei/nova4899r/romstage.c
View File

@ -36,19 +36,11 @@
static void main(unsigned long bist)
{
/* Initialize the serial console. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();
/* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}

6
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
View File

@ -58,11 +58,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
void main(unsigned long bist)
{
post_code(0x01);
@ -80,7 +75,6 @@ void main(unsigned long bist)
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
uart_init();
console_init();

3
src/mainboard/intel/d945gclf/romstage.c
View File

@ -201,9 +201,8 @@ void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
if (bist == 0) {
if (bist == 0)
enable_lapic();
}
ich7_enable_lpc();
early_superio_config_lpc47m15x();

3
src/mainboard/intel/eagleheights/romstage.c
View File

@ -138,9 +138,8 @@ void main(unsigned long bist)
}
};
if (bist == 0) {
if (bist == 0)
enable_lapic();
}
/* Setup the console */
i3100_enable_superio();

17
src/mainboard/intel/jarrell/romstage.c
View File

@ -45,12 +45,6 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
/*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
}
@ -59,10 +53,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Setup the console */
pc87427_disable_dev(CONSOLE_SERIAL_DEV);
@ -86,9 +79,8 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
}
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
@ -99,9 +91,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
for(i = 0; i < 1; i++)
dump_spd_registers();
}
#endif
disable_watchdogs();
power_down_reset_check();
@ -111,8 +102,6 @@ static void main(unsigned long bist)
ich5_watchdog_on();
#if 0
dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif

3
src/mainboard/intel/truxton/romstage.c
View File

@ -68,10 +68,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Set up the console */
i3100_enable_superio();

4
src/mainboard/intel/xe7501devkit/romstage.c
View File

@ -46,15 +46,13 @@ static void main(unsigned long bist)
},
};
if (bist == 0)
{
if (bist == 0) {
// Skip this if there was a built in self test failure
early_mtrr_init();
enable_lapic();
}
// Get the serial port running and print a welcome banner
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();

35
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@ -50,14 +50,12 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -69,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -84,7 +82,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// first node
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// second node
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
@ -92,23 +89,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the rom access for 4M */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -143,26 +135,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif

36
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@ -49,15 +49,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -69,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -92,23 +90,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the rom access for 4M */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -143,26 +136,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif

36
src/mainboard/iwill/dk8x/romstage.c
View File

@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@ -49,15 +49,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -69,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -92,23 +90,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the rom access for 4M */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -143,26 +136,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif

8
src/mainboard/jetway/j7f24/romstage.c
View File

@ -53,7 +53,8 @@ static void enable_mainboard_devices(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@ -94,20 +95,15 @@ void main(unsigned long bist)
uart_init();
console_init();
print_spew("In romstage.c:main()\n");
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
print_spew("Leaving romstage.c:main()\n");
}

12
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -59,9 +59,7 @@ static int smbus_read_byte(u32 device, u32 address);
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
@ -85,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@ -95,7 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}
@ -175,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb700_early_setup();
#if CONFIG_SET_FIDVID
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@ -196,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
#endif
rs780_htinit();

3
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -328,9 +328,8 @@ void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
if (bist == 0) {
if (bist == 0)
enable_lapic();
}
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);

26
src/mainboard/kontron/kt690/romstage.c
View File

@ -48,17 +48,9 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@ -76,9 +68,10 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
device_t dev;
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
@ -90,20 +83,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs690_dev8();
sb600_lpc_init();
dev=PNP_DEV(0x2e, W83627DHG_SP1);
w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
@ -137,8 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@ -150,7 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);

5
src/mainboard/lanner/em8510/romstage.c
View File

@ -77,15 +77,13 @@ void main(unsigned long bist)
print_pci_devices();
#endif
if(!bios_reset_detected()) {
if (!bios_reset_detected()) {
enable_smbus();
#if 1
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}
#if 0
@ -100,4 +98,3 @@ void main(unsigned long bist)
ram_check(0x80000000, 0x81000000);
#endif
}

1
src/mainboard/lippert/frontrunner/romstage.c
View File

@ -77,6 +77,7 @@ void main(unsigned long bist)
{.channel0 = {DIMM0, DIMM1}}
};
unsigned char temp;
SystemPreInit();
msr_init();

21
src/mainboard/msi/ms7135/romstage.c
View File

@ -50,15 +50,8 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
/* FIXME: Nothing to do? */
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* FIXME: Nothing to do? */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -100,22 +93,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -138,9 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();

6
src/mainboard/msi/ms7260/romstage.c
View File

@ -117,7 +117,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
@ -125,10 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
sio_setup();
/* Setup the MCP55. */
mcp55_enable_rom();
}
@ -186,11 +182,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.lo);
print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
{
msr_t msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");

22
src/mainboard/msi/ms9185/romstage.c
View File

@ -52,9 +52,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@ -85,7 +83,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* msi does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -116,22 +114,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
// post_code(0x32);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -177,26 +168,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif

11
src/mainboard/msi/ms9282/romstage.c
View File

@ -49,9 +49,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@ -82,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* msi does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
@ -138,12 +136,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
@ -177,7 +171,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();

17
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -51,10 +51,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -110,31 +107,23 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
u32 bsp_apicid = 0, val, wants_reset;
u8 reg;
u32 wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
post_code(0x32);

38
src/mainboard/newisys/khepri/romstage.c
View File

@ -35,14 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
/* Set the memreset low */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
else {
/* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
/* Set the memreset low. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines. */
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
/* Ensure the CPU has control of the memory lines. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@ -50,16 +49,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Set memreset high. */
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -69,7 +65,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* newisys khepri does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@ -88,26 +84,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

26
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -122,25 +116,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0);
@ -183,28 +171,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();

10
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -36,9 +36,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX1.C has no SMBus; the setup is hard-wired. */
static void cs5536_enable_smbus(void)
{
}
static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@ -114,11 +112,6 @@ static u8 spd_read_byte(u8 device, u8 address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
/** Early mainboard specific GPIO setup. */
static void mb_gpio_init(void)
{
}
void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
@ -137,7 +130,6 @@ void main(unsigned long bist)
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
mb_gpio_init();
uart_init();
console_init();

4
src/mainboard/pcengines/alix2d/romstage.c
View File

@ -36,9 +36,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX.2D has no SMBus; the setup is hard-wired. */
static void cs5536_enable_smbus(void)
{
}
static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"

3
src/mainboard/rca/rm4100/romstage.c
View File

@ -99,10 +99,9 @@ static void mb_early_setup(void)
void main(unsigned long bist)
{
if (bist == 0) {
if (memory_initialized()) {
if (memory_initialized())
hard_reset();
}
}
/* Set southbridge and superio gpios */
mb_gpio_init();

3
src/mainboard/roda/rk886ex/romstage.c
View File

@ -250,9 +250,8 @@ void main(unsigned long bist)
u32 reg32;
int boot_mode = 0;
if (bist == 0) {
if (bist == 0)
enable_lapic();
}
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);

22
src/mainboard/sunw/ultra40/romstage.c
View File

@ -28,9 +28,7 @@
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
#ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void)
@ -44,10 +42,7 @@ static void sio_gpio_setup(void)
}
#endif
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -57,7 +52,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@ -110,23 +105,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -147,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();

19
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -49,9 +49,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void dump_smbus_registers(void)
{
@ -183,25 +181,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@ -243,7 +235,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr = rdmsr(0xc0010042);
@ -251,15 +242,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
@ -268,7 +254,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
#endif

23
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -52,14 +52,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -85,6 +79,7 @@ static void sio_setup(void)
{
uint32_t dword;
uint8_t byte;
enable_smbus();
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
@ -115,25 +110,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@ -177,13 +166,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;

17
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -51,10 +51,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -111,30 +108,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
u32 wants_reset;
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
post_code(0x32);

16
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -117,6 +117,7 @@ static const u8 spd_addr[] = {
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
@ -156,31 +157,24 @@ static void write_GPIO(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
u32 wants_reset;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
post_code(0x32);

11
src/mainboard/supermicro/x6dai_g/romstage.c
View File

@ -60,10 +60,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Setup the console */
outb(0x87,0x2e);
@ -77,16 +76,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
if (dev == PCI_DEV_INVALID)
die("Missing 6300ESB?");
}
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
#endif
#if 0
print_pci_devices();
#endif
#if 1
@ -94,9 +90,8 @@ static void main(unsigned long bist)
#endif
#if 0
int i;
for(i = 0; i < 1; i++) {
for(i = 0; i < 1; i++)
dump_spd_registers();
}
#endif
disable_watchdogs();
sdram_initialize(ARRAY_SIZE(mch), mch);

19
src/mainboard/supermicro/x6dhe_g/romstage.c
View File

@ -49,12 +49,6 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
/*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
@ -63,10 +57,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Setup the console */
outb(0x87,0x2e);
@ -83,16 +76,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
if (dev == PCI_DEV_INVALID)
die("Missing esb6300?");
}
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
#endif
#if 0
print_pci_devices();
#endif
#if 1
@ -101,9 +91,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
for(i = 0; i < 1; i++)
dump_spd_registers();
}
#endif
disable_watchdogs();
// dump_ipmi_registers();
@ -111,8 +100,6 @@ static void main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif

17
src/mainboard/supermicro/x6dhe_g2/romstage.c
View File

@ -47,12 +47,6 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
/*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
@ -61,10 +55,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Setup the console */
outb(0x87,0x2e);
@ -81,16 +74,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
if (dev == PCI_DEV_INVALID) {
if (dev == PCI_DEV_INVALID)
die("Missing ich5r?");
}
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
#endif
#if 0
print_pci_devices();
#endif
#if 1
@ -99,9 +89,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
for(i = 0; i < 1; i++)
dump_spd_registers();
}
#endif
disable_watchdogs();
// dump_ipmi_registers();

11
src/mainboard/supermicro/x6dhr_ig/romstage.c
View File

@ -62,10 +62,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Setup the console */
outb(0x87,0x2e);
@ -82,16 +81,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
}
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
#endif
#if 0
print_pci_devices();
#endif
#if 1
@ -100,9 +96,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
for(i = 0; i < 1; i++)
dump_spd_registers();
}
#endif
disable_watchdogs();
// dump_ipmi_registers();

19
src/mainboard/supermicro/x6dhr_ig2/romstage.c
View File

@ -48,12 +48,6 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
/*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
*/
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
@ -62,10 +56,9 @@ static void main(unsigned long bist)
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
if (memory_initialized()) {
if (memory_initialized())
skip_romstage();
}
}
/* Setup the console */
outb(0x87,0x2e);
@ -82,16 +75,13 @@ static void main(unsigned long bist)
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
if (dev == PCI_DEV_INVALID) {
if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
}
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
#endif
#if 0
print_pci_devices();
#endif
#if 1
@ -100,9 +90,8 @@ static void main(unsigned long bist)
#if 0
// dump_spd_registers(&cpu[0]);
int i;
for(i = 0; i < 1; i++) {
for(i = 0; i < 1; i++)
dump_spd_registers();
}
#endif
disable_watchdogs();
// dump_ipmi_registers();
@ -110,8 +99,6 @@ static void main(unsigned long bist)
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif

20
src/mainboard/technexion/tim5690/romstage.c
View File

@ -47,17 +47,9 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@ -90,7 +82,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
@ -98,9 +89,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
technexion_post_code_init();
technexion_post_code(LED_MESSAGE_START);
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs690_dev8();
sb600_lpc_init();
@ -141,8 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@ -154,7 +143,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}

20
src/mainboard/technexion/tim8690/romstage.c
View File

@ -47,17 +47,9 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
/* called in raminit_f.c */
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
}
/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@ -88,14 +80,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
enable_rs690_dev8();
sb600_lpc_init();
@ -136,8 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
if( (cpuid1.edx & 0x6) == 0x6 ) {
if ((cpuid1.edx & 0x6) == 0x6 ) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@ -149,7 +138,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}

9
src/mainboard/televideo/tc7020/romstage.c
View File

@ -35,20 +35,11 @@
static void main(unsigned long bist)
{
/* Initialize the serial console. */
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();
/* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}

3
src/mainboard/thomson/ip1000/romstage.c
View File

@ -98,10 +98,9 @@ static void mb_early_setup(void)
void main(unsigned long bist)
{
if (bist == 0) {
if (memory_initialized()) {
if (memory_initialized())
hard_reset();
}
}
/* Set southbridge and superio gpios */
mb_gpio_init();

6
src/mainboard/traverse/geos/romstage.c
View File

@ -52,11 +52,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
static void mb_gpio_init(void)
{
/* Early mainboard specific GPIO setup. */
}
void main(unsigned long bist)
{
post_code(0x01);
@ -78,7 +73,6 @@ void main(unsigned long bist)
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
mb_gpio_init();
uart_init();
console_init();

9
src/mainboard/tyan/s2735/romstage.c
View File

@ -46,9 +46,8 @@ void main(unsigned long bist)
},
};
if (bist == 0) {
if (bist == 0)
enable_lapic();
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -57,15 +56,12 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if(bios_reset_detected()) {
if (bios_reset_detected())
hard_reset();
}
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
#endif
#if 0
dump_smbus_registers();
#endif
@ -79,4 +75,3 @@ void main(unsigned long bist)
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
}

26
src/mainboard/tyan/s2850/romstage.c
View File

@ -29,28 +29,23 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -86,16 +81,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
@ -128,4 +119,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

26
src/mainboard/tyan/s2875/romstage.c
View File

@ -29,28 +29,23 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -97,15 +92,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -135,6 +127,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
}

26
src/mainboard/tyan/s2880/romstage.c
View File

@ -29,28 +29,23 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -97,16 +92,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -138,4 +129,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

32
src/mainboard/tyan/s2881/romstage.c
View File

@ -28,28 +28,23 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -78,24 +73,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
@ -131,8 +120,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
@ -151,4 +138,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

24
src/mainboard/tyan/s2882/romstage.c
View File

@ -29,28 +29,23 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -97,15 +92,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

33
src/mainboard/tyan/s2885/romstage.c
View File

@ -28,28 +28,23 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -59,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@ -78,26 +73,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the amd8111 */
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

34
src/mainboard/tyan/s2891/romstage.c
View File

@ -25,18 +25,9 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void memreset_setup(void) { }
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -46,7 +37,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
@ -92,23 +83,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
@ -135,9 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@ -152,8 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
@ -162,12 +144,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}

24
src/mainboard/tyan/s2892/romstage.c
View File

@ -25,14 +25,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -42,7 +36,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@ -84,23 +78,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
// post_code(0x32);
@ -123,9 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@ -143,4 +130,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

37
src/mainboard/tyan/s2895/romstage.c
View File

@ -19,38 +19,31 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/mtrr.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static void memreset_setup(void) { }
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static void sio_gpio_setup(void)
{
unsigned value;
/*Enable onboard scsi*/
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c,
(1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@ -59,7 +52,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@ -113,23 +106,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -151,9 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_other_cores_started(bsp_apicid);
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@ -172,4 +158,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}

27
src/mainboard/tyan/s2912/romstage.c
View File

@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -123,30 +117,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
uart_init();
/* Halt if there was a built in self test failure */
@ -181,26 +167,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif

17
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -52,10 +52,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -117,29 +114,22 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
u32 wants_reset;
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
post_code(0x32);
@ -256,4 +246,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}

24
src/mainboard/tyan/s4880/romstage.c
View File

@ -28,23 +28,22 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
@ -52,6 +51,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x01, device);
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
#if 0
static inline void change_i2c_mux(unsigned device)
{
@ -73,7 +73,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -110,7 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
},
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
{
.node_id = 2,
@ -140,15 +139,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();

30
src/mainboard/tyan/s4882/romstage.c
View File

@ -27,23 +27,22 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
if (is_cpu_pre_c0())
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
else
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
@ -57,6 +56,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
#if 0
static inline void change_i2c_mux(unsigned device)
{
@ -81,7 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c" /* tyan does not want the default */
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@ -112,24 +112,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
int needs_reset;
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
amd8111_enable_rom();
}
if (bist == 0) {
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
}
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@ -169,6 +163,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
post_cache_as_ram();
}

14
src/mainboard/via/epia-cn/romstage.c
View File

@ -47,7 +47,8 @@ static void enable_mainboard_devices(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@ -87,21 +88,10 @@ void main(unsigned long bist)
enable_vt8235_serial();
uart_init();
console_init();
print_spew("In romstage.c:main()\n");
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
print_spew("Leaving romstage.c:main()\n");
}

13
src/mainboard/via/epia-m/romstage.c
View File

@ -72,9 +72,7 @@ static void main(unsigned long bist)
{
device_t dev;
/*
* Enable VGA; 32MB buffer.
*/
/* Enable VGA; 32MB buffer. */
pci_write_config8(0, 0xe1, 0xdd);
/*
@ -83,9 +81,8 @@ static void main(unsigned long bist)
*/
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_6305), 0);
if (dev != PCI_DEV_INVALID) {
if (dev != PCI_DEV_INVALID)
pci_write_config8(dev, 0x15, 0x1c);
}
enable_vt8235_serial();
uart_init();
@ -122,12 +119,8 @@ static void main(unsigned long bist)
}
#endif
if (bist == 0) {
print_debug(" Doing MTRR init.\n");
if (bist == 0)
early_mtrr_init();
}
//dump_pci_devices();
print_spew("Leaving romstage.c:main()\n");
}

11
src/mainboard/via/epia-m700/romstage.c
View File

@ -448,17 +448,6 @@ void main(unsigned long bist)
/* This fix does help vx800!, but vx855 doesn't need this. */
/* smbus_fixup(&ctrl); */
if (bist == 0) {
/*
* CAR needs MTRR until memory is ok, so disable this
* early_mtrr_init() call.
*/
#if 0
print_debug("doing early_mtrr\n");
early_mtrr_init();
#endif
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);

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