mb/google/drallion: Add new SPD files for drallion

Add new SPD files for drallion:
1. Hynix H5AN8G6NDJR-XNC
2. Samung K4AAG165WA-BCWE
3. Samung K4A8G165WC-BCWE

BUG=b:148642500
TEST=Compile successfully and check SPD info in cbmem log.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ian Feng 2020-02-06 18:42:31 +08:00 committed by Patrick Georgi
parent bfe0948f7d
commit 7bac50e824
5 changed files with 101 additions and 2 deletions

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@ -0,0 +1,32 @@
23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20
0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53
36 44 4A 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD
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@ -0,0 +1,32 @@
23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
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80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36
35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -0,0 +1,32 @@
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36
35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE
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@ -23,6 +23,9 @@ SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b11001
SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011
SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011
SPD_SOURCES += micron_dimm_MT40A1G16KD-062EE # 0b11010
SPD_SOURCES += hynix_dimm_H5AN8G6NDJR-XNC # 0b01100
SPD_SOURCES += samsung_dimm_K4AAG165WA-BCWE # 0b00000
SPD_SOURCES += samsung_dimm_K4A8G165WC-BCWE # 0b00100
bootblock-y += gpio.c
ramstage-y += gpio.c

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@ -21,8 +21,8 @@
/* Use spd_index array to save mem_id */
static const int spd_index[32] = {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
10, 0, 0, 0, 11, 0, 0, 0,
0, 0, 0, 0, 9, 0, 0, 0,
0, 4, 3, 6, 1, 0, 0, 0,
0, 5, 8, 7, 2, 0, 0, 0
};