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soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macro 

Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.

TEST=Timeless build results in identical image for Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-09-08 00:37:30 +02:00 committed by Felix Held
parent fd63e11f71
commit 7bbde76014
4 changed files with 17 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/amd/cezanne/early_fch.c
View File

@ -15,10 +15,10 @@
/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
{ PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL },
{ PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL },
{ PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL },
{ PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL },
I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
};
static void reset_i2c_peripherals(void)

7
src/soc/amd/common/block/include/amdblocks/i2c.h
View File

@ -35,6 +35,13 @@ struct soc_i2c_scl_pin {
uint8_t pin_mask;
};
/* Macro to populate the elements of the array of soc_i2c_scl_pin in the SoC code */
#define I2C_RESET_SCL_PIN(pin_name, pin_mask_value) \
{ \
.pin = PAD_CFG_STRUCT(pin_name, pin_name ## _IOMUX_GPIOxx, PAD_OUTPUT(HIGH)), \
.pin_mask = pin_mask_value, \
}
/**
* Information about I2C peripherals that need to be reset.
* @i2c_scl_reset_mask: Bit mask of I2C buses that need to be reset based on the device tree

4
src/soc/amd/picasso/early_fch.c
View File

@ -17,8 +17,8 @@
/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
{ PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL },
{ PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL },
I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
/* I2C4 is a peripheral device only */
};

8
src/soc/amd/stoneyridge/bootblock.c
View File

@ -30,10 +30,10 @@
/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
{ PAD_GPO(I2C0_SCL_PIN, HIGH), GPIO_I2C0_SCL },
{ PAD_GPO(I2C1_SCL_PIN, HIGH), GPIO_I2C1_SCL },
{ PAD_GPO(I2C2_SCL_PIN, HIGH), GPIO_I2C2_SCL },
{ PAD_GPO(I2C3_SCL_PIN, HIGH), GPIO_I2C3_SCL },
I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
};
/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */