mb/google/dedede: Add dedede mainboard
Add mainboard stubs for Dedede. More functionalities will be added later. BUG=b:144768001 TEST=Build test. Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38277 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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config BOARD_GOOGLE_BASEBOARD_DEDEDE
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def_bool n
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select SOC_INTEL_JASPERLAKE
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if BOARD_GOOGLE_BASEBOARD_DEDEDE
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config BASEBOARD_DEDEDE_LAPTOP
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def_bool n
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select SYSTEM_TYPE_LAPTOP
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config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config MAINBOARD_DIR
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string
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default "google/dedede"
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config MAINBOARD_FAMILY
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string
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default "Google_Dedede" if BOARD_GOOGLE_DEDEDE
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config MAINBOARD_PART_NUMBER
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string
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default "dedede" if BOARD_GOOGLE_DEDEDE
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config MAX_CPUS
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int
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default 4
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config UART_FOR_CONSOLE
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int
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default 2
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endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
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config BOARD_GOOGLE_DEDEDE
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bool "Dedede"
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select BOARD_GOOGLE_BASEBOARD_DEDEDE
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select BASEBOARD_DEDEDE_LAPTOP
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select BOARD_ROMSIZE_KB_32768
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bootblock-y += bootblock.c
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ramstage-y += mainboard.c
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subdirs-y += variants/baseboard
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
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Vendor name: Google
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Board name: Dedede
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Category: laptop
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Authors.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <bootblock_common.h>
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void bootblock_mainboard_init(void)
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{
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/* TODO: Perform mainboard initialization */
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}
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FLASH@0xfe000000 0x2000000 {
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SI_ALL@0x0 0x500000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x4ff000
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}
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SI_BIOS@0x500000 0x1b00000 {
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# Place RW_LEGACY at the start of BIOS region such that the rest
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# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
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# SPI flash only the top 16MiB actually gets memory mapped.
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RW_LEGACY(CBFS)@0x0 0xf00000
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RW_SECTION_A@0xf00000 0x3e0000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x3cffc0
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RW_FWID_A@0x3dffc0 0x40
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}
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RW_SECTION_B@0x12e0000 0x3e0000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x3cffc0
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RW_FWID_B@0x3dffc0 0x40
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}
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RW_MISC@0x16c0000 0x40000 {
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UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
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RECOVERY_MRC_CACHE@0x0 0x10000
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RW_MRC_CACHE@0x10000 0x20000
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}
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RW_ELOG(PRESERVE)@0x30000 0x4000
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RW_SHARED@0x34000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD(PRESERVE)@0x38000 0x2000
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RW_NVRAM(PRESERVE)@0x3a000 0x6000
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}
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# Make WP_RO region align with SPI vendor
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# memory protected range specification.
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WP_RO@0x1700000 0x400000 {
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RO_VPD(PRESERVE)@0x0 0x4000
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RO_SECTION@0x4000 0x3fc000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0x3000
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COREBOOT(CBFS)@0x4000 0x3f8000
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}
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}
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}
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Authors.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <device/device.h>
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static void mainboard_init(void *chip_info)
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{
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/* TODO: Perform mainboard initialization */
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}
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static void mainboard_enable(struct device *dev)
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{
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/* TODO: Enable mainboard */
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Authors.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <fsp/api.h>
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#include <soc/romstage.h>
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void mainboard_memory_init_params(FSPM_UPD *memupd)
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{
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/* ToDo : Fill FSP-M memory params */
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}
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chip soc/intel/tigerlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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end
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Authors.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef __BASEBOARD_GPIO_H__
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#define __BASEBOARD_GPIO_H__
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#endif /* __BASEBOARD_GPIO_H__ */
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2020 The coreboot project Authors.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef __BASEBOARD_VARIANTS_H__
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#define __BASEBOARD_VARIANTS_H__
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#include <soc/gpio.h>
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#include <stdint.h>
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#endif /*__BASEBOARD_VARIANTS_H__ */
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