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mb/google/brya/var/taeko: Enable CPU PCIE RP 1 

Modify settings to enable CPU PCIE RP 1 according to schematics.

BUG=b:205504257
TEST=emerge-brya coreboot and can successfully boot with ssd and emmc.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Joey Peng 2021-11-08 15:21:32 +08:00 committed by Tim Wawrzynczak
parent ca69152579
commit 7bca1e474c
2 changed files with 30 additions and 2 deletions
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25
src/mainboard/google/brya/variants/taeko/gpio.c
View File

@ -46,8 +46,8 @@ static const struct pad_config override_gpio_table[] = {
/* D3 : ISH_GP3 ==> NC */ /* D3 : ISH_GP3 ==> NC */
PAD_NC(GPP_D3, NONE), PAD_NC(GPP_D3, NONE),
/* D5 : SRCCLKREQ0# ==> NC */ /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
PAD_NC(GPP_D5, NONE), PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D9 : ISH_SPI_CS# ==> NC */ /* D9 : ISH_SPI_CS# ==> NC */
PAD_NC(GPP_D9, NONE), PAD_NC(GPP_D9, NONE),
/* D10 : ISH_SPI_CLK ==> NC */ /* D10 : ISH_SPI_CLK ==> NC */
@ -174,6 +174,27 @@ static const struct pad_config early_gpio_table[] = {
* B4 is programmed here so that it is sequenced after EN_PP3300_SSD. * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
*/ */
PAD_CFG_GPO(GPP_B4, 1, DEEP), PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* CPU PCIe VGPIO for PEG60 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
}; };
const struct pad_config *variant_gpio_override_table(size_t *num) const struct pad_config *variant_gpio_override_table(size_t *num)

7
src/mainboard/google/brya/variants/taeko/overridetree.cb
View File

@ -221,6 +221,13 @@ chip soc/intel/alderlake
device generic 0 alias dptf_policy on end device generic 0 alias dptf_policy on end
end end
end end
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 0,
.clk_src = 0,
}"
end
device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp0 off end
device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp1 off end
device ref tbt_pcie_rp2 off end device ref tbt_pcie_rp2 off end