AMD S3: Leverage the public SPI routine
Remove the old, unflexible code for storing S3 data in SPI flash. Refer to flashrom. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Zheng Bao
Marc Jones
parent
78a1667cbc
commit
7bcffa511d
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@ -41,7 +41,8 @@
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#include "agesawrapper.h"
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#ifndef __PRE_RAM__
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#include "spi.h"
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#include <spi.h>
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#include <spi_flash.h>
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#endif
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void restore_mtrr(void)
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@ -151,14 +152,18 @@ void move_stack_high_mem(void)
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void OemAgesaSaveMtrr(void)
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{
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#ifndef __PRE_RAM__
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u32 spi_address;
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msr_t msr_data;
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device_t dev;
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u32 nvram_pos = S3_DATA_MTRR_POS;
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u32 i;
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struct spi_flash *flash;
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dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
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spi_address = pci_read_config32(dev, 0xA0) & ~0x1F;
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spi_init();
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flash = spi_flash_probe(0, 0, 0, 0);
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if (!flash) {
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printk(BIOS_DEBUG, "Could not find SPI device\n");
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return;
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}
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr_data = rdmsr(SYS_CFG);
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@ -167,28 +172,29 @@ void OemAgesaSaveMtrr(void)
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/* Fixed MTRRs */
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msr_data = rdmsr(0x250);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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msr_data = rdmsr(0x258);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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msr_data = rdmsr(0x259);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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for (i = 0x268; i < 0x270; i++) {
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msr_data = rdmsr(i);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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}
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@ -200,35 +206,33 @@ void OemAgesaSaveMtrr(void)
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/* Variable MTRRs */
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for (i = 0x200; i < 0x210; i++) {
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msr_data = rdmsr(i);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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}
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/* SYS_CFG */
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msr_data = rdmsr(0xC0010010);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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/* TOM */
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msr_data = rdmsr(0xC001001A);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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/* TOM2 */
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msr_data = rdmsr(0xC001001D);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo);
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flash->write(flash, nvram_pos, 4, &msr_data.lo);
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nvram_pos += 4;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi);
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flash->write(flash, nvram_pos, 4, &msr_data.hi);
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nvram_pos += 4;
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write_spi_status((u8 *)spi_address, 0x3c);
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spi_write_disable((u8 *) spi_address);
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#endif
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}
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@ -251,9 +255,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
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{
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u32 pos = S3_DATA_VOLATILE_POS;
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u32 spi_address, data;
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u32 data;
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u32 nvram_pos;
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device_t dev;
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struct spi_flash *flash;
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if (S3DataType == S3DataTypeNonVolatile) {
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pos = S3_DATA_NONVOLATILE_POS;
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@ -261,39 +265,27 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
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pos = S3_DATA_VOLATILE_POS;
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}
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dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
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spi_address = pci_read_config32(dev, 0xA0) & ~0x1F;
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spi_init();
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flash = spi_flash_probe(0, 0, 0, 0);
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if (!flash) {
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printk(BIOS_DEBUG, "Could not find SPI device\n");
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/* Dont make flow stop. */
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return AGESA_SUCCESS;
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}
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/* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */
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read_spi_id((u8 *) spi_address);
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write_spi_status((u8 *)spi_address, 0);
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if (S3DataType == S3DataTypeNonVolatile) {
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sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS);
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flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000);
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} else {
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sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS);
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sector_erase_spi((u8 *) spi_address,
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S3_DATA_VOLATILE_POS + 0x1000);
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sector_erase_spi((u8 *) spi_address,
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S3_DATA_VOLATILE_POS + 0x2000);
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sector_erase_spi((u8 *) spi_address,
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S3_DATA_VOLATILE_POS + 0x3000);
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sector_erase_spi((u8 *) spi_address,
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S3_DATA_VOLATILE_POS + 0x4000);
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sector_erase_spi((u8 *) spi_address,
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S3_DATA_VOLATILE_POS + 0x5000);
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flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000);
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}
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nvram_pos = 0;
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dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize);
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flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize);
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for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) {
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data = *(u32 *) (Data + nvram_pos);
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dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4,
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*(u32 *) (Data + nvram_pos));
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flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos));
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}
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/* write_spi_status((u8 *)spi_address, 0x3c); */
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/* spi_write_disable((u8 *) spi_address); */
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return AGESA_SUCCESS;
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}
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@ -14,3 +14,7 @@ source src/southbridge/amd/sb800/Kconfig
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source src/southbridge/amd/cimx/Kconfig
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source src/southbridge/amd/agesa/Kconfig
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source src/southbridge/amd/sr5650/Kconfig
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config SPI_FLASH
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bool
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default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA
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@ -16,203 +16,107 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <arch/io.h>
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#include <spi.h>
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#include <device/device.h>
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#include "spi.h"
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#include <device/pci.h>
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#include <device/pci_ops.h>
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void execute_command(volatile u8 * spi_address)
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static u32 spibar;
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static void reset_internal_fifo_pointer(void)
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{
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*(spi_address + 2) |= 1;
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}
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void wait4command_complete(volatile u8 * spi_address)
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{
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// while (*(spi_address + 2) & 1)
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while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80))
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printk(BIOS_DEBUG, "wait4CommandComplete\n");
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}
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void reset_internal_fifo_pointer(volatile u8 * spi_address)
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{
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u8 val;
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do {
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*(spi_address + 2) |= 0x10;
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val = *(spi_address + 0xd);
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} while (val & 0x7);
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write8(spibar + 2, read8(spibar + 2) | 0x10);
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} while (read8(spibar + 0xD) & 0x7);
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}
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u8 read_spi_status(volatile u8 * spi_address)
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static void execute_command(void)
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{
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u8 val;
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*spi_address = 0x05;
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*(spi_address + 1) = 0x21;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = 0x0; /* dummy */
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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reset_internal_fifo_pointer(spi_address);
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val = *(spi_address + 0xC);
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val = *(spi_address + 0xC);
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val = *(spi_address + 0xC);
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return val;
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write8(spibar + 2, read8(spibar + 2) | 1);
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while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
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}
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void wait4flashpart_ready(volatile u8 * spi_address)
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void spi_init()
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{
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while (read_spi_status(spi_address) & 1) ;
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
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spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
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}
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void write_spi_status(volatile u8 * spi_address, u8 status)
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int spi_xfer(struct spi_slave *slave, const void *dout,
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unsigned int bitsout, void *din, unsigned int bitsin)
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{
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*spi_address = 0x50; /* EWSR */
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*(spi_address + 1) = 0; /* RxByte=TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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/* First byte is cmd which can not being sent through FIFO. */
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u8 cmd = *(u8 *)dout++;
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u8 readoffby1;
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u8 readwrite;
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u8 bytesout, bytesin;
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u8 count;
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*spi_address = 0x01; /* WRSR */
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*(spi_address + 1) = 0x01;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = status;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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bitsout -= 8;
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bytesout = bitsout / 8;
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bytesin = bitsin / 8;
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read_spi_status(spi_address);
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}
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readoffby1 = bytesout ? 0 : 1;
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void read_spi_id(volatile u8 * spi_address)
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{
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u8 mid = 0, did = 0;
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*spi_address = 0x90;
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*(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = 0;
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*(spi_address + 0xC) = 0;
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*(spi_address + 0xC) = 0;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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reset_internal_fifo_pointer(spi_address);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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readwrite = (bytesin + readoffby1) << 4 | bytesout;
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write8(spibar + 1, readwrite);
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write8(spibar + 0, cmd);
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mid = *(spi_address + 0xC);
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did = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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}
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void spi_write_enable(volatile u8 * spi_address)
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{
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*spi_address = 0x06; /* Write Enable */
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*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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}
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void spi_write_disable(volatile u8 * spi_address)
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{
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*spi_address = 0x04; /* Write Enable */
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*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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}
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void sector_erase_spi(volatile u8 * spi_address, u32 address)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x20;
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*(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void chip_erase_spi(volatile u8 * spi_address)
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{
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spi_write_enable(spi_address);
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*spi_address = 0xC7;
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*(spi_address + 1) = 0x00;
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void byte_program(volatile u8 * spi_address, u32 address, u32 data)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 4;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data)
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{
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u8 i;
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/*
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* printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data);
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*/
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for (i = 0; i < 4; i++) {
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 4;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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data >>= 8;
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address++;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
reset_internal_fifo_pointer();
|
||||
for (count = 0; count < bytesout; count++, dout++) {
|
||||
write8(spibar + 0x0C, *(u8 *)dout);
|
||||
}
|
||||
|
||||
reset_internal_fifo_pointer();
|
||||
execute_command();
|
||||
|
||||
reset_internal_fifo_pointer();
|
||||
/* Skip the bytes we sent. */
|
||||
for (count = 0; count < bytesout; count++) {
|
||||
cmd = read8(spibar + 0x0C);
|
||||
}
|
||||
|
||||
reset_internal_fifo_pointer();
|
||||
for (count = 0; count < bytesin; count++, din++) {
|
||||
*(u8 *)din = read8(spibar + 0x0C);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dword_program(volatile u8 * spi_address, u32 address, u32 data)
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
spi_write_enable(spi_address);
|
||||
*spi_address = 0x02;
|
||||
*(spi_address + 1) = 0x0 << 4 | 7;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = (address >> 16) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 8) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 0) & 0xFF;
|
||||
*(spi_address + 0xC) = data & 0xFF;
|
||||
*(spi_address + 0xC) = (data >> 8) & 0xFF;
|
||||
*(spi_address + 0xC) = (data >> 16) & 0xFF;
|
||||
*(spi_address + 0xC) = (data >> 24) & 0xFF;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
}
|
||||
|
||||
void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data)
|
||||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
spi_write_enable(spi_address);
|
||||
*address = data;
|
||||
wait4flashpart_ready(spi_address);
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
}
|
||||
|
||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
||||
unsigned int max_hz, unsigned int mode)
|
||||
{
|
||||
struct spi_slave *slave = malloc(sizeof(*slave));
|
||||
|
||||
if (!slave) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
memset(slave, 0, sizeof(*slave));
|
||||
|
||||
return slave;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _HUDSON_CIMX_SPI_H_
|
||||
#define _HUDSON_CIMX_SPI_H_
|
||||
|
||||
void execute_command(volatile u8 * spi_address);
|
||||
void wait4command_complete(volatile u8 * spi_address);
|
||||
void reset_internal_fifo_pointer(volatile u8 * spi_address);
|
||||
u8 read_spi_status(volatile u8 * spi_address);
|
||||
void wait4flashpart_ready(volatile u8 * spi_address);
|
||||
void write_spi_status(volatile u8 * spi_address, u8 status);
|
||||
void read_spi_id(volatile u8 * spi_address);
|
||||
void spi_write_enable(volatile u8 * spi_address);
|
||||
void spi_write_disable(volatile u8 * spi_address);
|
||||
void sector_erase_spi(volatile u8 * spi_address, u32 address);
|
||||
void chip_erase_spi(volatile u8 * spi_address);
|
||||
void byte_program(volatile u8 * spi_address, u32 address, u32 data);
|
||||
void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data);
|
||||
void dword_program(volatile u8 * spi_address, u32 address, u32 data);
|
||||
void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data);
|
||||
|
||||
#endif
|
||||
|
|
@ -16,201 +16,107 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <console/console.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <arch/io.h>
|
||||
#include <spi.h>
|
||||
#include <device/device.h>
|
||||
#include "SBPLATFORM.h"
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
static u32 spibar;
|
||||
|
||||
void execute_command(volatile u8 * spi_address)
|
||||
static void reset_internal_fifo_pointer(void)
|
||||
{
|
||||
*(spi_address + 2) |= 1;
|
||||
}
|
||||
|
||||
void wait4command_complete(volatile u8 * spi_address)
|
||||
{
|
||||
while (*(spi_address + 2) & 1)
|
||||
printk(BIOS_DEBUG, "wait4CommandComplete\n");
|
||||
}
|
||||
|
||||
void reset_internal_fifo_pointer(volatile u8 * spi_address)
|
||||
{
|
||||
u8 val;
|
||||
|
||||
do {
|
||||
*(spi_address + 2) |= 0x10;
|
||||
val = *(spi_address + 0xd);
|
||||
} while (val & 0x7);
|
||||
write8(spibar + 2, read8(spibar + 2) | 0x10);
|
||||
} while (read8(spibar + 0xD) & 0x7);
|
||||
}
|
||||
|
||||
u8 read_spi_status(volatile u8 * spi_address)
|
||||
static void execute_command(void)
|
||||
{
|
||||
u8 val;
|
||||
*spi_address = 0x05;
|
||||
*(spi_address + 1) = 0x11;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = 0x0; /* dummy */
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
val = *(spi_address + 0xC);
|
||||
val = *(spi_address + 0xC);
|
||||
return val;
|
||||
write8(spibar + 2, read8(spibar + 2) | 1);
|
||||
|
||||
while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
|
||||
}
|
||||
|
||||
void wait4flashpart_ready(volatile u8 * spi_address)
|
||||
void spi_init()
|
||||
{
|
||||
while (read_spi_status(spi_address) & 1) ;
|
||||
device_t dev;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
|
||||
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
|
||||
}
|
||||
|
||||
void write_spi_status(volatile u8 * spi_address, u8 status)
|
||||
int spi_xfer(struct spi_slave *slave, const void *dout,
|
||||
unsigned int bitsout, void *din, unsigned int bitsin)
|
||||
{
|
||||
*spi_address = 0x50; /* EWSR */
|
||||
*(spi_address + 1) = 0; /* RxByte=TxByte=0 */
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
/* First byte is cmd which can not being sent through FIFO. */
|
||||
u8 cmd = *(u8 *)dout++;
|
||||
u8 readoffby1;
|
||||
u8 readwrite;
|
||||
u8 bytesout, bytesin;
|
||||
u8 count;
|
||||
|
||||
*spi_address = 0x01; /* WRSR */
|
||||
*(spi_address + 1) = 0x01;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = status;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
bitsout -= 8;
|
||||
bytesout = bitsout / 8;
|
||||
bytesin = bitsin / 8;
|
||||
|
||||
read_spi_status(spi_address);
|
||||
}
|
||||
readoffby1 = bytesout ? 0 : 1;
|
||||
|
||||
void read_spi_id(volatile u8 * spi_address)
|
||||
{
|
||||
u8 mid = 0, did = 0;
|
||||
*spi_address = 0x90;
|
||||
*(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = 0;
|
||||
*(spi_address + 0xC) = 0;
|
||||
*(spi_address + 0xC) = 0;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
mid = *(spi_address + 0xC);
|
||||
printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
|
||||
mid = *(spi_address + 0xC);
|
||||
printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
|
||||
mid = *(spi_address + 0xC);
|
||||
printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
|
||||
readwrite = (bytesin + readoffby1) << 4 | bytesout;
|
||||
write8(spibar + 1, readwrite);
|
||||
write8(spibar + 0, cmd);
|
||||
|
||||
mid = *(spi_address + 0xC);
|
||||
did = *(spi_address + 0xC);
|
||||
printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
|
||||
}
|
||||
|
||||
void spi_write_enable(volatile u8 * spi_address)
|
||||
{
|
||||
*spi_address = 0x06; /* Write Enable */
|
||||
*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
}
|
||||
void spi_write_disable(volatile u8 * spi_address)
|
||||
{
|
||||
*spi_address = 0x04; /* Write Enable */
|
||||
*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
}
|
||||
|
||||
void sector_erase_spi(volatile u8 * spi_address, u32 address)
|
||||
{
|
||||
spi_write_enable(spi_address);
|
||||
*spi_address = 0x20;
|
||||
*(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */
|
||||
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = (address >> 16) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 8) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 0) & 0xFF;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
}
|
||||
|
||||
void chip_erase_spi(volatile u8 * spi_address)
|
||||
{
|
||||
spi_write_enable(spi_address);
|
||||
*spi_address = 0xC7;
|
||||
*(spi_address + 1) = 0x00;
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
}
|
||||
|
||||
void byte_program(volatile u8 * spi_address, u32 address, u32 data)
|
||||
{
|
||||
spi_write_enable(spi_address);
|
||||
*spi_address = 0x02;
|
||||
*(spi_address + 1) = 0x0 << 4 | 4;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = (address >> 16) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 8) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 0) & 0xFF;
|
||||
*(spi_address + 0xC) = data & 0xFF;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
}
|
||||
|
||||
void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data)
|
||||
{
|
||||
u8 i;
|
||||
/*
|
||||
* printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data);
|
||||
*/
|
||||
for (i = 0; i < 4; i++) {
|
||||
spi_write_enable(spi_address);
|
||||
*spi_address = 0x02;
|
||||
*(spi_address + 1) = 0x0 << 4 | 4;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = (address >> 16) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 8) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 0) & 0xFF;
|
||||
*(spi_address + 0xC) = data & 0xFF;
|
||||
data >>= 8;
|
||||
address++;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
reset_internal_fifo_pointer();
|
||||
for (count = 0; count < bytesout; count++, dout++) {
|
||||
write8(spibar + 0x0C, *(u8 *)dout);
|
||||
}
|
||||
|
||||
reset_internal_fifo_pointer();
|
||||
execute_command();
|
||||
|
||||
reset_internal_fifo_pointer();
|
||||
/* Skip the bytes we sent. */
|
||||
for (count = 0; count < bytesout; count++) {
|
||||
cmd = read8(spibar + 0x0C);
|
||||
}
|
||||
|
||||
reset_internal_fifo_pointer();
|
||||
for (count = 0; count < bytesin; count++, din++) {
|
||||
*(u8 *)din = read8(spibar + 0x0C);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
int spi_claim_bus(struct spi_slave *slave)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dword_program(volatile u8 * spi_address, u32 address, u32 data)
|
||||
void spi_release_bus(struct spi_slave *slave)
|
||||
{
|
||||
spi_write_enable(spi_address);
|
||||
*spi_address = 0x02;
|
||||
*(spi_address + 1) = 0x0 << 4 | 7;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
*(spi_address + 0xC) = (address >> 16) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 8) & 0xFF;
|
||||
*(spi_address + 0xC) = (address >> 0) & 0xFF;
|
||||
*(spi_address + 0xC) = data & 0xFF;
|
||||
*(spi_address + 0xC) = (data >> 8) & 0xFF;
|
||||
*(spi_address + 0xC) = (data >> 16) & 0xFF;
|
||||
*(spi_address + 0xC) = (data >> 24) & 0xFF;
|
||||
reset_internal_fifo_pointer(spi_address);
|
||||
execute_command(spi_address);
|
||||
wait4command_complete(spi_address);
|
||||
wait4flashpart_ready(spi_address);
|
||||
}
|
||||
|
||||
void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data)
|
||||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
spi_write_enable(spi_address);
|
||||
*address = data;
|
||||
wait4flashpart_ready(spi_address);
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
}
|
||||
|
||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
|
||||
unsigned int max_hz, unsigned int mode)
|
||||
{
|
||||
struct spi_slave *slave = malloc(sizeof(*slave));
|
||||
|
||||
if (!slave) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
memset(slave, 0, sizeof(*slave));
|
||||
|
||||
return slave;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,42 +0,0 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SB800_CIMX_SPI_H_
|
||||
#define _SB800_CIMX_SPI_H_
|
||||
|
||||
void execute_command(volatile u8 * spi_address);
|
||||
void wait4command_complete(volatile u8 * spi_address);
|
||||
void reset_internal_fifo_pointer(volatile u8 * spi_address);
|
||||
u8 read_spi_status(volatile u8 * spi_address);
|
||||
void wait4flashpart_ready(volatile u8 * spi_address);
|
||||
void write_spi_status(volatile u8 * spi_address, u8 status);
|
||||
void read_spi_id(volatile u8 * spi_address);
|
||||
void spi_write_enable(volatile u8 * spi_address);
|
||||
void sector_erase_spi(volatile u8 * spi_address, u32 address);
|
||||
void chip_erase_spi(volatile u8 * spi_address);
|
||||
void byte_program(volatile u8 * spi_address, u32 address, u32 data);
|
||||
void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data);
|
||||
void dword_program(volatile u8 * spi_address, u32 address, u32 data);
|
||||
void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue