nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devices

Set max_mem_clock_mhz in devicetree to 933Mhz.
Allows to run the memory at up to DDR3-1866.

The same frequency was allowed within the first vendor bios,
but Lenovo than decided to limit it to DDR3-1333.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

The RAM is now running at DDR3-1600 instead of DDR3-1333.
This gives about 4% performance increase in glmark2 using the
Intel GPU.

Change-Id: If15be497402d84a2778f0434b6381a64eda832d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15158
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Patrick Rudolph 2016-06-11 18:39:35 +02:00 committed by Martin Roth
parent 4089a17cb9
commit 7bddd30e94
8 changed files with 26 additions and 1 deletions

View File

@ -18,6 +18,9 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B chip cpu/intel/socket_rPGA988B
device lapic 0 on end device lapic 0 on end

View File

@ -17,6 +17,9 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B chip cpu/intel/socket_rPGA988B
device lapic 0 on end device lapic 0 on end

View File

@ -17,6 +17,9 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989 chip cpu/intel/socket_rPGA989
device lapic 0 on end device lapic 0 on end

View File

@ -18,6 +18,9 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B chip cpu/intel/socket_rPGA988B
device lapic 0 on end device lapic 0 on end

View File

@ -18,6 +18,9 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989 chip cpu/intel/socket_rPGA989
device lapic 0 on end device lapic 0 on end

View File

@ -18,6 +18,9 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989 chip cpu/intel/socket_rPGA989
device lapic 0 on end device lapic 0 on end

View File

@ -18,6 +18,9 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"
# Override fuse bits that hard-code the value to 666 Mhz
register "max_mem_clock_mhz" = "933"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989 chip cpu/intel/socket_rPGA989
device lapic 0 on end device lapic 0 on end

View File

@ -4374,7 +4374,11 @@ static unsigned int get_mem_min_tck(void)
} }
return DEFAULT_TCK; return DEFAULT_TCK;
} else { } else {
if (cfg->max_mem_clock_mhz >= 800) if (cfg->max_mem_clock_mhz >= 1066)
return TCK_1066MHZ;
else if (cfg->max_mem_clock_mhz >= 933)
return TCK_933MHZ;
else if (cfg->max_mem_clock_mhz >= 800)
return TCK_800MHZ; return TCK_800MHZ;
else if (cfg->max_mem_clock_mhz >= 666) else if (cfg->max_mem_clock_mhz >= 666)
return TCK_666MHZ; return TCK_666MHZ;