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nb/x4x/raminit_ddr2: Refactor clock configuration slightly 

The result is shorter and (IMHO) more readable code.

Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Jonathan Neuschäfer 2018-02-12 12:00:40 +01:00 committed by Martin Roth
parent cb304c1d85
commit 7be74dbb38
1 changed files with 14 additions and 17 deletions
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31
src/northbridge/intel/x4x/raminit_ddr2.c
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@ -722,23 +722,20 @@ static void dll_ddr2(struct sysinfo *s)
} }
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { const struct dll_setting *setting;
clkset0(i, &dll_setting_667[CLKSET0]);
clkset1(i, &dll_setting_667[CLKSET1]); if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)
ctrlset0(i, &dll_setting_667[CTRL0]); setting = dll_setting_667;
ctrlset1(i, &dll_setting_667[CTRL1]); else
ctrlset2(i, &dll_setting_667[CTRL2]); setting = dll_setting_800;
ctrlset3(i, &dll_setting_667[CTRL3]);
cmdset(i, &dll_setting_667[CMD]); clkset0(i, &setting[CLKSET0]);
} else { clkset1(i, &setting[CLKSET1]);
clkset0(i, &dll_setting_800[CLKSET0]); ctrlset0(i, &setting[CTRL0]);
clkset1(i, &dll_setting_800[CLKSET1]); ctrlset1(i, &setting[CTRL1]);
ctrlset0(i, &dll_setting_800[CTRL0]); ctrlset2(i, &setting[CTRL2]);
ctrlset1(i, &dll_setting_800[CTRL1]); ctrlset3(i, &setting[CTRL3]);
ctrlset2(i, &dll_setting_800[CTRL2]); cmdset(i, &setting[CMD]);
ctrlset3(i, &dll_setting_800[CTRL3]);
cmdset(i, &dll_setting_800[CMD]);
}
} }
// XXX if not async mode // XXX if not async mode