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soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree 

The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this GPIO to 1 or 0 will not change the HDA
GPIO configuration; it will make the sound work when set to 1,
or not work when set to 0.

Remove the incorrect comment and make the UPD configurable from the
devicetree.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Sean Rhodes 2023-01-06 10:50:53 +00:00 committed by Felix Held
parent fd4ad29f18
commit 7bfc256eeb
2 changed files with 2 additions and 7 deletions
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1
src/soc/intel/alderlake/chip.h
View File

@ -348,6 +348,7 @@ struct soc_intel_alderlake_config {
uint16_t sata_ports_dito_val[8]; uint16_t sata_ports_dito_val[8];
/* Audio related */ /* Audio related */
uint8_t pch_hda_audio_link_hda_enable;
uint8_t pch_hda_dsp_enable; uint8_t pch_hda_dsp_enable;
/* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */

8
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -242,13 +242,7 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode;
m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency;
m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable;
/* m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable;
* All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
* configure GPIO pads for audio. Mainboard is expected to perform all GPIO
* configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
* configuration for audio pads.
*/
m_cfg->PchHdaAudioLinkHdaEnable = 0;
memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));