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mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb 

Based on schematic and gpio table of voxel, generate gpio settings
and overridetree.cb for voxel.

BUG=b:157879197,b:155062762
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Verify that the image-voxel.bin is generated successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit is contained in:
David Wu 2020-06-23 20:33:46 +08:00 committed by Patrick Georgi
parent 63358eaff6
commit 7c040adc8c
2 changed files with 356 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

241
src/mainboard/google/volteer/variants/voxel/gpio.c
View File

@ -5,19 +5,243 @@
#include <commonlib/helpers.h>
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
static const struct pad_config override_gpio_table[] = {
/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
PAD_CFG_GPO(GPP_A7, 1, DEEP),
/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
PAD_CFG_GPO(GPP_A8, 1, DEEP),
/* A10 : I2S2_RXD ==> EN_SPKR_PA */
PAD_CFG_GPO(GPP_A10, 1, DEEP),
/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
PAD_CFG_GPO(GPP_A13, 1, DEEP),
/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* A18 : DDSP_HPDB ==> HDMI_HPD */
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_A21, 1, DEEP),
/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
PAD_CFG_GPO(GPP_A22, 1, DEEP),
/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
/* B2 : VRALERT# ==> NC(TP18) */
PAD_NC(GPP_B2, NONE),
/* B3 : CPU_GP2 ==> PEN_DET_ODL */
PAD_CFG_GPI(GPP_B3, NONE, DEEP),
/* B5 : ISH_I2C0_CVF_SDA */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
/* B6 : ISH_I2C0_CVF_SCL */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
/* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
PAD_NC(GPP_B23, DN_20K),
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> EN_USB_CAM_PWR */
PAD_CFG_GPO(GPP_C1, 1, DEEP),
/* C2 : SMBALERT# ==> GPP_C2_STRAP */
PAD_NC(GPP_C2, DN_20K),
/* C3 : SML0CLK ==> USB4_SMB_SCL */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
/* C4 : SML0DATA ==> USB4_SMB_SDA */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
/* C5 : SML0ALERT# ==> NC(TP93) */
PAD_NC(GPP_C5, DN_20K),
/* C7 : SML1DATA ==> EN_USI_CHARGE */
PAD_CFG_GPO(GPP_C7, 1, DEEP),
/* C10 : UART0_RTS# ==> USI_RST_L */
PAD_CFG_GPO(GPP_C10, 1, DEEP),
/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* C20 : UART2_RXD ==> FPMCU_INT_L */
PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
PAD_CFG_GPO(GPP_C22, 0, DEEP),
/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
/* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
/* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7),
/* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7),
/* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */
PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7),
/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_D16, 1, DEEP),
/* D17 : ISH_GP4 ==> EN_CVF_PWR */
PAD_CFG_GPO(GPP_D17, 1, DEEP),
/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
PAD_CFG_GPO(GPP_E3, 1, DEEP),
/* E7 : CPU_GP1 ==> USI_INT */
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
/* E8 : SPI1_CS1# ==> SLP_S0IX */
PAD_CFG_GPO(GPP_E8, 0, DEEP),
/* E10 : SPI1_CS# ==> NC(TP94508) */
PAD_NC(GPP_E10, NONE),
/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
PAD_CFG_GPI(GPP_E11, NONE, DEEP),
/* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_E12, 1, DEEP),
/* E13 : SPI1_MOSI_IO0 ==> NC(TP94507) */
PAD_NC(GPP_E13, NONE),
/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
/* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP),
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
/* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
/* F7 : GPPF7_STRAP */
PAD_NC(GPP_F7, DN_20K),
/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
PAD_CFG_GPO(GPP_F11, 1, DEEP),
/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
PAD_CFG_GPO(GPP_F13, 1, DEEP),
/* F14 : GSXDIN ==> SAR0_INT_L */
PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE),
/* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
/* H0 : GPPH0_BOOT_STRAP1 */
PAD_NC(GPP_H0, DN_20K),
/* H1 : GPPH1_BOOT_STRAP2 */
PAD_NC(GPP_H1, DN_20K),
/* H2 : GPPH2_BOOT_STRAP3 */
PAD_NC(GPP_H2, DN_20K),
/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
PAD_CFG_GPO(GPP_H3, 1, DEEP),
/* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */
PAD_CFG_GPI(GPP_H12, NONE, DEEP),
/* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
PAD_CFG_GPI(GPP_H13, NONE, DEEP),
/* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */
PAD_CFG_GPI(GPP_H15, NONE, DEEP),
/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */
PAD_CFG_GPI(GPP_H19, NONE, DEEP),
/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
/* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
/* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
};
const struct pad_config *variant_base_gpio_table(size_t *num)
const struct pad_config *variant_override_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
/* B11 : PMCALERT# ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
/* C0 : SMBCLK ==> EN_PP3300_WLAN */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
PAD_CFG_GPO(GPP_C22, 0, DEEP),
/* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_E12, 1, DEEP),
};
const struct pad_config *variant_early_gpio_table(size_t *num)
@ -25,12 +249,3 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
};
const struct cros_gpio *variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}

128
src/mainboard/google/volteer/variants/voxel/overridetree.cb
View File

@ -1,4 +1,132 @@
chip soc/intel/tigerlake
device domain 0 on
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Headset Codec""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_count" = "1"
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on
end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "0"
register "imon_slot_no" = "1"
register "uid" = "0"
register "desc" = ""Right Speaker Amp""
register "name" = ""MAXR""
device i2c 31 on
end
end
chip drivers/i2c/max98373
register "vmon_slot_no" = "2"
register "imon_slot_no" = "3"
register "uid" = "1"
register "desc" = ""Left Speaker Amp""
register "name" = ""MAXL""
device i2c 32 on
end
end
end # I2C #0 0xA0E8
device pci 15.1 on
chip drivers/i2c/hid
register "generic.hid" = ""GDIX0000""
register "generic.desc" = ""Goodix Touchscreen""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
register "generic.reset_delay_ms" = "120"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 14 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""ELAN90FC""
register "generic.desc" = ""ELAN Touchscreen""
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
register "generic.reset_delay_ms" = "20"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
end # I2C1 0xA0E9
device pci 15.2 on
chip drivers/i2c/sx9310
register "desc" = ""SAR0 Proximity Sensor""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "0"
register "reg_prox_ctrl0" = "0x10"
register "reg_prox_ctrl1" = "0x00"
register "reg_prox_ctrl2" = "0x84"
register "reg_prox_ctrl3" = "0x0e"
register "reg_prox_ctrl4" = "0x07"
register "reg_prox_ctrl5" = "0xc6"
register "reg_prox_ctrl6" = "0x20"
register "reg_prox_ctrl7" = "0x0d"
register "reg_prox_ctrl8" = "0x8d"
register "reg_prox_ctrl9" = "0x43"
register "reg_prox_ctrl10" = "0x1f"
register "reg_prox_ctrl11" = "0x00"
register "reg_prox_ctrl12" = "0x00"
register "reg_prox_ctrl13" = "0x00"
register "reg_prox_ctrl14" = "0x00"
register "reg_prox_ctrl15" = "0x00"
register "reg_prox_ctrl16" = "0x00"
register "reg_prox_ctrl17" = "0x00"
register "reg_prox_ctrl18" = "0x00"
register "reg_prox_ctrl19" = "0x00"
register "reg_sar_ctrl0" = "0x50"
register "reg_sar_ctrl1" = "0x8a"
register "reg_sar_ctrl2" = "0x3c"
device i2c 28 on end
end
end # I2C2 0xA0EA
device pci 19.1 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
register "wake" = "GPE0_DW2_15"
register "probed" = "1"
device i2c 15 on end
end
end # I2C5 0xA0C6
device pci 1f.2 hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/con
register "usb2_port_number" = "9"
register "usb3_port_number" = "1"
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 0 on end
end
chip drivers/intel/pmc_mux/con
register "usb2_port_number" = "4"
register "usb3_port_number" = "2"
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 1 on end
end
end
end
end # PMC
end
end