mb/google/volteer/var/voxel: Update gpio settings and overridetree.cb
Based on schematic and gpio table of voxel, generate gpio settings and overridetree.cb for voxel. BUG=b:157879197,b:155062762 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Verify that the image-voxel.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit is contained in:
David Wu
Patrick Georgi
parent
63358eaff6
commit
7c040adc8c
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@ -5,19 +5,243 @@
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#include <commonlib/helpers.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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static const struct pad_config override_gpio_table[] = {
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/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
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PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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/* A10 : I2S2_RXD ==> EN_SPKR_PA */
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PAD_CFG_GPO(GPP_A10, 1, DEEP),
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/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_A13, 1, DEEP),
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/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
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PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* A18 : DDSP_HPDB ==> HDMI_HPD */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
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PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_A21, 1, DEEP),
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/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
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PAD_CFG_GPO(GPP_A22, 1, DEEP),
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/* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */
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PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
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/* B2 : VRALERT# ==> NC(TP18) */
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PAD_NC(GPP_B2, NONE),
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/* B3 : CPU_GP2 ==> PEN_DET_ODL */
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PAD_CFG_GPI(GPP_B3, NONE, DEEP),
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/* B5 : ISH_I2C0_CVF_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* B6 : ISH_I2C0_CVF_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
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/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
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PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
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PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
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/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
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PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
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/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
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PAD_NC(GPP_B23, DN_20K),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> EN_USB_CAM_PWR */
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PAD_CFG_GPO(GPP_C1, 1, DEEP),
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/* C2 : SMBALERT# ==> GPP_C2_STRAP */
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PAD_NC(GPP_C2, DN_20K),
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/* C3 : SML0CLK ==> USB4_SMB_SCL */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* C4 : SML0DATA ==> USB4_SMB_SDA */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* C5 : SML0ALERT# ==> NC(TP93) */
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PAD_NC(GPP_C5, DN_20K),
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/* C7 : SML1DATA ==> EN_USI_CHARGE */
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PAD_CFG_GPO(GPP_C7, 1, DEEP),
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/* C10 : UART0_RTS# ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* C20 : UART2_RXD ==> FPMCU_INT_L */
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PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */
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PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7),
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/* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
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PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7),
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/* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */
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PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7),
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/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
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PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
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/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
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PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
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PAD_CFG_GPO(GPP_D16, 1, DEEP),
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/* D17 : ISH_GP4 ==> EN_CVF_PWR */
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PAD_CFG_GPO(GPP_D17, 1, DEEP),
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/* E1 : SPI1_IO2 ==> PEN_DET_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
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/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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/* E3 : CPU_GP0 ==> USI_REPORT_EN */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E7 : CPU_GP1 ==> USI_INT */
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PAD_CFG_GPI(GPP_E7, NONE, DEEP),
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/* E8 : SPI1_CS1# ==> SLP_S0IX */
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PAD_CFG_GPO(GPP_E8, 0, DEEP),
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/* E10 : SPI1_CS# ==> NC(TP94508) */
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PAD_NC(GPP_E10, NONE),
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/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
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PAD_CFG_GPI(GPP_E11, NONE, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_E12, 1, DEEP),
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/* E13 : SPI1_MOSI_IO0 ==> NC(TP94507) */
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PAD_NC(GPP_E13, NONE),
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/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT),
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/* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */
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PAD_CFG_TERM_GPO(GPP_E17, 1, DN_20K, DEEP),
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/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
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PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
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/* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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/* F7 : GPPF7_STRAP */
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PAD_NC(GPP_F7, DN_20K),
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/* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */
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PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH),
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/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
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PAD_CFG_GPO(GPP_F11, 1, DEEP),
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/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
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PAD_CFG_GPO(GPP_F13, 1, DEEP),
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/* F14 : GSXDIN ==> SAR0_INT_L */
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PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE),
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/* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
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/* F19 : SRCCLKREQ6# ==> WLAN_INT_L */
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PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
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/* H0 : GPPH0_BOOT_STRAP1 */
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PAD_NC(GPP_H0, DN_20K),
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/* H1 : GPPH1_BOOT_STRAP2 */
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PAD_NC(GPP_H1, DN_20K),
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/* H2 : GPPH2_BOOT_STRAP3 */
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PAD_NC(GPP_H2, DN_20K),
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/* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H3, 1, DEEP),
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/* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SAR1_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SAR1_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */
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PAD_CFG_GPI(GPP_H12, NONE, DEEP),
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/* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */
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PAD_CFG_GPI(GPP_H13, NONE, DEEP),
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/* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */
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PAD_CFG_GPI(GPP_H15, NONE, DEEP),
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/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
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PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
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/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
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/* H19 : TIME_SYNC0 ==> PCH_CAM_VSYNC */
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PAD_CFG_GPI(GPP_H19, NONE, DEEP),
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/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
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/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
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/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
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/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
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/* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
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/* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),
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/* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),
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/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
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/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
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/* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
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/* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
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/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
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/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
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/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
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PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
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};
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};
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const struct pad_config *variant_base_gpio_table(size_t *num)
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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{
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*num = ARRAY_SIZE(gpio_table);
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*num = ARRAY_SIZE(override_gpio_table);
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return gpio_table;
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return override_gpio_table;
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}
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}
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/* Early pad configuration in bootblock */
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* B11 : PMCALERT# ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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/* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_E12, 1, DEEP),
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};
|
};
|
||||||
|
|
||||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||||
|
|
@ -25,12 +249,3 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||||
*num = ARRAY_SIZE(early_gpio_table);
|
*num = ARRAY_SIZE(early_gpio_table);
|
||||||
return early_gpio_table;
|
return early_gpio_table;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct cros_gpio cros_gpios[] = {
|
|
||||||
};
|
|
||||||
|
|
||||||
const struct cros_gpio *variant_cros_gpios(size_t *num)
|
|
||||||
{
|
|
||||||
*num = ARRAY_SIZE(cros_gpios);
|
|
||||||
return cros_gpios;
|
|
||||||
}
|
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,132 @@
|
||||||
chip soc/intel/tigerlake
|
chip soc/intel/tigerlake
|
||||||
device domain 0 on
|
device domain 0 on
|
||||||
|
device pci 15.0 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""10EC5682""
|
||||||
|
register "name" = ""RT58""
|
||||||
|
register "desc" = ""Headset Codec""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)"
|
||||||
|
# Set the jd_src to RT5668_JD1 for jack detection
|
||||||
|
register "property_count" = "1"
|
||||||
|
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||||
|
register "property_list[0].name" = ""realtek,jd-src""
|
||||||
|
register "property_list[0].integer" = "1"
|
||||||
|
device i2c 1a on
|
||||||
|
end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/max98373
|
||||||
|
register "vmon_slot_no" = "0"
|
||||||
|
register "imon_slot_no" = "1"
|
||||||
|
register "uid" = "0"
|
||||||
|
register "desc" = ""Right Speaker Amp""
|
||||||
|
register "name" = ""MAXR""
|
||||||
|
device i2c 31 on
|
||||||
|
end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/max98373
|
||||||
|
register "vmon_slot_no" = "2"
|
||||||
|
register "imon_slot_no" = "3"
|
||||||
|
register "uid" = "1"
|
||||||
|
register "desc" = ""Left Speaker Amp""
|
||||||
|
register "name" = ""MAXL""
|
||||||
|
device i2c 32 on
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end # I2C #0 0xA0E8
|
||||||
|
device pci 15.1 on
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""GDIX0000""
|
||||||
|
register "generic.desc" = ""Goodix Touchscreen""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "generic.reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
|
||||||
|
register "generic.reset_delay_ms" = "120"
|
||||||
|
register "generic.reset_off_delay_ms" = "3"
|
||||||
|
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
|
||||||
|
register "generic.enable_delay_ms" = "12"
|
||||||
|
register "generic.has_power_resource" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 14 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""ELAN90FC""
|
||||||
|
register "generic.desc" = ""ELAN Touchscreen""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "generic.reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
|
||||||
|
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
|
||||||
|
register "generic.reset_delay_ms" = "20"
|
||||||
|
register "generic.has_power_resource" = "1"
|
||||||
|
register "generic.disable_gpio_export_in_crs" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 10 on end
|
||||||
|
end
|
||||||
|
end # I2C1 0xA0E9
|
||||||
|
device pci 15.2 on
|
||||||
|
chip drivers/i2c/sx9310
|
||||||
|
register "desc" = ""SAR0 Proximity Sensor""
|
||||||
|
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
|
||||||
|
register "speed" = "I2C_SPEED_FAST"
|
||||||
|
register "uid" = "0"
|
||||||
|
register "reg_prox_ctrl0" = "0x10"
|
||||||
|
register "reg_prox_ctrl1" = "0x00"
|
||||||
|
register "reg_prox_ctrl2" = "0x84"
|
||||||
|
register "reg_prox_ctrl3" = "0x0e"
|
||||||
|
register "reg_prox_ctrl4" = "0x07"
|
||||||
|
register "reg_prox_ctrl5" = "0xc6"
|
||||||
|
register "reg_prox_ctrl6" = "0x20"
|
||||||
|
register "reg_prox_ctrl7" = "0x0d"
|
||||||
|
register "reg_prox_ctrl8" = "0x8d"
|
||||||
|
register "reg_prox_ctrl9" = "0x43"
|
||||||
|
register "reg_prox_ctrl10" = "0x1f"
|
||||||
|
register "reg_prox_ctrl11" = "0x00"
|
||||||
|
register "reg_prox_ctrl12" = "0x00"
|
||||||
|
register "reg_prox_ctrl13" = "0x00"
|
||||||
|
register "reg_prox_ctrl14" = "0x00"
|
||||||
|
register "reg_prox_ctrl15" = "0x00"
|
||||||
|
register "reg_prox_ctrl16" = "0x00"
|
||||||
|
register "reg_prox_ctrl17" = "0x00"
|
||||||
|
register "reg_prox_ctrl18" = "0x00"
|
||||||
|
register "reg_prox_ctrl19" = "0x00"
|
||||||
|
register "reg_sar_ctrl0" = "0x50"
|
||||||
|
register "reg_sar_ctrl1" = "0x8a"
|
||||||
|
register "reg_sar_ctrl2" = "0x3c"
|
||||||
|
device i2c 28 on end
|
||||||
|
end
|
||||||
|
end # I2C2 0xA0EA
|
||||||
|
device pci 19.1 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""ELAN0000""
|
||||||
|
register "desc" = ""ELAN Touchpad""
|
||||||
|
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
|
||||||
|
register "wake" = "GPE0_DW2_15"
|
||||||
|
register "probed" = "1"
|
||||||
|
device i2c 15 on end
|
||||||
|
end
|
||||||
|
end # I2C5 0xA0C6
|
||||||
|
device pci 1f.2 hidden
|
||||||
|
# The pmc_mux chip driver is a placeholder for the
|
||||||
|
# PMC.MUX device in the ACPI hierarchy.
|
||||||
|
chip drivers/intel/pmc_mux
|
||||||
|
device generic 0 on
|
||||||
|
chip drivers/intel/pmc_mux/con
|
||||||
|
register "usb2_port_number" = "9"
|
||||||
|
register "usb3_port_number" = "1"
|
||||||
|
# SBU is fixed, HSL follows CC
|
||||||
|
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||||
|
device generic 0 on end
|
||||||
|
end
|
||||||
|
chip drivers/intel/pmc_mux/con
|
||||||
|
register "usb2_port_number" = "4"
|
||||||
|
register "usb3_port_number" = "2"
|
||||||
|
# SBU is fixed, HSL follows CC
|
||||||
|
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||||
|
device generic 1 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end # PMC
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue