mb/google/cherry: Pass reset gpio parameter to BL31
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=execute `echo b > /proc/sysrq-trigger` to reboot system Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bl31.h>
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#include <bootmode.h>
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#include <bootmode.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <delay.h>
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#include <delay.h>
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@ -12,6 +13,10 @@
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#include <soc/regulator.h>
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#include <soc/regulator.h>
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#include <soc/usb.h>
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#include <soc/usb.h>
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#include "gpio.h"
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#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
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DEFINE_BITFIELD(MSDC0_DRV, 29, 0)
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DEFINE_BITFIELD(MSDC0_DRV, 29, 0)
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DEFINE_BITFIELD(MSDC1_DRV, 17, 0)
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DEFINE_BITFIELD(MSDC1_DRV, 17, 0)
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DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24)
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DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24)
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@ -31,6 +36,17 @@ enum {
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MSDC1_GPIO_MODE1_BASE = 0x100053e0,
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MSDC1_GPIO_MODE1_BASE = 0x100053e0,
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};
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};
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static void register_reset_to_bl31(void)
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{
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static struct bl_aux_param_gpio param_reset = {
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.h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
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.gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH },
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};
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param_reset.gpio.index = GPIO_RESET.id;
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register_bl31_aux_param(¶m_reset.h);
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}
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static void configure_emmc(void)
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static void configure_emmc(void)
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{
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{
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void *gpio_base = (void *)IOCFG_TL_BASE;
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void *gpio_base = (void *)IOCFG_TL_BASE;
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@ -107,6 +123,8 @@ static void mainboard_init(struct device *dev)
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configure_emmc();
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configure_emmc();
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configure_sdcard();
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configure_sdcard();
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setup_usb_host();
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setup_usb_host();
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register_reset_to_bl31();
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}
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}
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static void mainboard_enable(struct device *dev)
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static void mainboard_enable(struct device *dev)
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