Addition of Family12/SB900 wrapper code
This change adds the wrapper code for the AMD Family12 cpus and the AMD Hudson-2 (SB900) southbridge to the cpu, northbridge and southbridge folders respectively. Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/53 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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source src/cpu/amd/agesa/family12/Kconfig
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source src/cpu/amd/agesa/family14/Kconfig
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@ -16,4 +16,5 @@
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
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subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
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@ -0,0 +1,74 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config CPU_AMD_AGESA_FAMILY12
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bool
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select PCI_IO_CFG_EXT
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config CPU_ADDR_BITS
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int
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default 36
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depends on CPU_AMD_AGESA_FAMILY12
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config CPU_SOCKET_TYPE
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hex
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default 0x10
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depends on CPU_AMD_AGESA_FAMILY12
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# DDR2 and REG
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config DIMM_SUPPORT
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hex
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default 0x0104
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depends on CPU_AMD_AGESA_FAMILY12
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config EXT_RT_TBL_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_FAMILY12
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config EXT_CONF_SUPPORT
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bool
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default n
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depends on CPU_AMD_AGESA_FAMILY12
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config CBB
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hex
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default 0x0
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depends on CPU_AMD_AGESA_FAMILY12
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config CDB
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hex
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default 0x18
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depends on CPU_AMD_AGESA_FAMILY12
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config XIP_ROM_BASE
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hex
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default 0xfff80000
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depends on CPU_AMD_AGESA_FAMILY12
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config XIP_ROM_SIZE
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hex
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default 0x80000
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depends on CPU_AMD_AGESA_FAMILY12
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config HAVE_INIT_TIMER
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bool
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default y
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depends on CPU_AMD_AGESA_FAMILY12
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@ -0,0 +1,326 @@
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#*****************************************************************************
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#
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# Copyright (c) 2011, Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# * Neither the name of Advanced Micro Devices, Inc. nor the names of
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# its contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#*****************************************************************************
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ramstage-y += chip_name.c
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driver-y += model_12_init.c
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AGESA_ROOT = ../../../../vendorcode/amd/agesa/f12
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agesa_lib_src = $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c
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agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c
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agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c
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agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuCommonF12Utilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12BrandId.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12BrandIdFm1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12BrandIdFs1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12CacheDefaults.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12Dmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12EarlyNbPstateInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12MsrTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12PciTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12PerCorePciTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12PowerCheck.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12PowerMgmtSystemTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12PowerPlane.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12Pstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12SoftwareThermal.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12Utilities.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/F12C6State.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/F12Cpb.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/F12IoCstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c
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#agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/LN/F12LnEarlySamples.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/LN/F12LnEquivalenceTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/LN/F12LnLogicalIdTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x12/LN/F12LnMicrocodePatchTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCoreLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuL3Features.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuLowPwrPstate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSwC1e.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/PreserveMailbox.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxConfigData.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxGmcInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtEnvPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxRegisterAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/Family/LN/F12GfxServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbConfigData.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInit.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEnv.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtLatePost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtPost.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbPowerMgmt.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbSmuLib.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/LN/F12NbServices.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/LN/F12NbSmu.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbFuseTable.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbLclkDpm.c
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agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEnv.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtLatePost.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtPost.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieLateInit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortLateInit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Feature/PciePowerGate.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam12/htNbFam12.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam12/htNbUtilitiesFam12.c
|
||||
#agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsCtrl.c
|
||||
#agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsLib.c
|
||||
#agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Control/IdsNvToCmos.c
|
||||
#agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Debug/IdsDebug.c
|
||||
#agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Family/0x12/IdsF12AllService.c
|
||||
#agesa_lib_src += $(AGESA_ROOT)/Proc/IDS/Perf/IdsPerf.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/LN/masln3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/LN/mauln3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/LN/mmflowln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mndctln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnflowln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnidendimmln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnmctln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnotln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnphyln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnprotoln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnregln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/LN/mnS3ln.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mplribt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mplrnlr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mplrnpr.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmaxfreq.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpmr0.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpodtpat.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprc10opspd.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprc2ibt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mprtt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mpsao.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/LN/mprln3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/LN/mpsln3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/LN/mpuln3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrcSeedTrain.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtlrdimm3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitRecovery.c
|
||||
agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitReset.c
|
||||
|
||||
romstage-y += $(agesa_lib_src)
|
||||
ramstage-y += $(agesa_lib_src)
|
||||
|
||||
subdirs-y += ../../mtrr
|
||||
subdirs-y += ../../../x86/tsc
|
||||
subdirs-y += ../../../x86/lapic
|
||||
subdirs-y += ../../../x86/cache
|
||||
subdirs-y += ../../../x86/mtrr
|
||||
subdirs-y += ../../../x86/pae
|
||||
subdirs-y += ../../../x86/smm
|
||||
|
||||
ramstage-y += apic_timer.c
|
||||
|
||||
cpu_incs += $(src)/cpu/amd/agesa/family12/cache_as_ram.inc
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <delay.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
|
||||
* pre-memory init (__PRE_RAM__). Don't use init_timer() and udelay is
|
||||
* redirected to udelay_tsc().
|
||||
*/
|
||||
|
||||
|
||||
void init_timer(void)
|
||||
{
|
||||
/* Set the apic timer to no interrupts and periodic mode */
|
||||
lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
|
||||
|
||||
/* Set the divider to 1, no divider */
|
||||
lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
|
||||
|
||||
/* Set the initial counter to 0xffffffff */
|
||||
lapic_write(LAPIC_TMICT, 0xffffffff);
|
||||
}
|
||||
|
||||
|
||||
void udelay(u32 usecs)
|
||||
{
|
||||
u32 start, value, ticks;
|
||||
/* Calculate the number of ticks to run, our FSB runs a 200Mhz */
|
||||
ticks = usecs * 200;
|
||||
start = lapic_read(LAPIC_TMCCT);
|
||||
do {
|
||||
value = lapic_read(LAPIC_TMCCT);
|
||||
} while((start - value) < ticks);
|
||||
|
||||
}
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* AMD Generic Encapsulated Software Architecture
|
||||
*
|
||||
* $Workfile:: cache_as_ram.inc
|
||||
*
|
||||
* Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "gcccar.inc"
|
||||
|
||||
/*
|
||||
* XMM map:
|
||||
* xmm0: BIST
|
||||
* xmm1: backup ebx -- cpu_init_detected
|
||||
*/
|
||||
|
||||
.code32
|
||||
.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
|
||||
|
||||
cache_as_ram_setup:
|
||||
|
||||
post_code(0xa0)
|
||||
|
||||
/* enable SSE2 128bit instructions */
|
||||
/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
|
||||
|
||||
movl %cr4, %eax
|
||||
orl $(3<<9), %eax
|
||||
movl %eax, %cr4
|
||||
|
||||
/* Get the cpu_init_detected */
|
||||
mov $1, %eax
|
||||
cpuid
|
||||
shr $24, %ebx
|
||||
|
||||
/* Save the BIST result */
|
||||
cvtsi2sd %ebp, %xmm0
|
||||
|
||||
/* for normal part %ebx already contain cpu_init_detected from fallback call */
|
||||
|
||||
/* Save the cpu_init_detected */
|
||||
cvtsi2sd %ebx, %xmm1
|
||||
|
||||
post_code(0xa1)
|
||||
AMD_ENABLE_STACK
|
||||
|
||||
post_code(0xa1)
|
||||
|
||||
/* Restore the BIST result */
|
||||
cvtsd2si %xmm0, %edx
|
||||
|
||||
/* Restore the cpu_init_detected */
|
||||
cvtsd2si %xmm1, %ebx
|
||||
|
||||
pushl %ebx /* init detected */
|
||||
pushl %edx /* bist */
|
||||
call cache_as_ram_main
|
||||
|
||||
/* Should never see this postcode */
|
||||
post_code(0xaf)
|
||||
stop:
|
||||
jmp stop
|
||||
|
||||
disable_cache_as_ram:
|
||||
/* Save return stack */
|
||||
cvtsi2sd %esp, %xmm0
|
||||
|
||||
AMD_DISABLE_STACK
|
||||
|
||||
/* Restore the return stack */
|
||||
cvtsd2si %xmm0, %esp
|
||||
|
||||
ret
|
||||
|
||||
cache_as_ram_setup_out:
|
||||
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
extern struct chip_operations cpu_amd_agesa_family12_ops;
|
||||
|
||||
struct cpu_amd_agesa_family12_config {
|
||||
};
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations cpu_amd_agesa_family12_ops = {
|
||||
CHIP_NAME("AMD CPU Family 12h")
|
||||
};
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/pae.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/amd/multicore.h>
|
||||
#include <cpu/amd/amdfam12.h>
|
||||
|
||||
#define MCI_STATUS 0x401
|
||||
|
||||
msr_t rdmsr_amd(u32 index)
|
||||
{
|
||||
msr_t result;
|
||||
__asm__ __volatile__(
|
||||
"rdmsr"
|
||||
:"=a"(result.lo), "=d"(result.hi)
|
||||
:"c"(index), "D"(0x9c5a203a)
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
void wrmsr_amd(u32 index, msr_t msr)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"wrmsr"
|
||||
: /* No outputs */
|
||||
:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
|
||||
);
|
||||
}
|
||||
|
||||
static void model_12_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n");
|
||||
|
||||
u8 i;
|
||||
msr_t msr;
|
||||
struct node_core_id id;
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
u32 siblings;
|
||||
#endif
|
||||
|
||||
// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
|
||||
// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
|
||||
|
||||
/* Turn on caching if we haven't already */
|
||||
x86_enable_cache();
|
||||
amd_setup_mtrrs();
|
||||
x86_mtrr_check();
|
||||
|
||||
disable_cache();
|
||||
|
||||
/* zero the machine check error status registers */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for (i = 0; i < 5; i++) {
|
||||
wrmsr(MCI_STATUS + (i * 4), msr);
|
||||
}
|
||||
|
||||
enable_cache();
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
/* Set the processor name string */
|
||||
// init_processor_name();
|
||||
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS == 1
|
||||
siblings = cpuid_ecx(0x80000008) & 0xff;
|
||||
|
||||
if (siblings > 0) {
|
||||
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
|
||||
msr.lo |= 1 << 28;
|
||||
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
|
||||
|
||||
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
|
||||
msr.hi |= 1 << (33 - 32);
|
||||
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
|
||||
}
|
||||
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
|
||||
#endif
|
||||
|
||||
/* DisableCf8ExtCfg */
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.hi &= ~(1 << (46 - 32));
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
|
||||
|
||||
/* Write protect SMM space with SMMLOCK. */
|
||||
msr = rdmsr(HWCR_MSR);
|
||||
msr.lo |= (1 << 0);
|
||||
wrmsr(HWCR_MSR, msr);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = model_12_init,
|
||||
};
|
||||
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */
|
||||
{ X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */
|
||||
{ X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */
|
||||
{ X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct cpu_driver model_12 __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef CPU_AMD_FAM12_H
|
||||
#define CPU_AMD_FAM12_H
|
||||
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
#define HWCR_MSR 0xC0010015
|
||||
#define NB_CFG_MSR 0xC001001f
|
||||
#define LS_CFG_MSR 0xC0011020
|
||||
#define IC_CFG_MSR 0xC0011021
|
||||
#define DC_CFG_MSR 0xC0011022
|
||||
#define BU_CFG_MSR 0xC0011023
|
||||
#define BU_CFG2_MSR 0xC001102A
|
||||
|
||||
#define CPU_ID_FEATURES_MSR 0xC0011004
|
||||
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
|
||||
|
||||
msr_t rdmsr_amd(u32 index);
|
||||
void wrmsr_amd(u32 index, msr_t msr);
|
||||
|
||||
//#if defined(__GNUC__)
|
||||
//// it can be used to get unitid and coreid it running only
|
||||
//struct node_core_id get_node_core_id(u32 nb_cfg_54);
|
||||
//struct node_core_id get_node_core_id_x(void);
|
||||
//#endif
|
||||
|
||||
#if defined(__PRE_RAM__)
|
||||
void wait_all_core0_started(void);
|
||||
void wait_all_other_cores_started(u32 bsp_apicid);
|
||||
void wait_all_aps_started(u32 bsp_apicid);
|
||||
void allow_all_aps_stop(u32 bsp_apicid);
|
||||
#endif
|
||||
u32 get_initial_apicid(void);
|
||||
|
||||
#endif /* CPU_AMD_FAM12_H */
|
|
@ -332,6 +332,29 @@
|
|||
#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396
|
||||
#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699
|
||||
|
||||
#define PCI_DEVICE_ID_ATI_SB900_LPC 0x780E
|
||||
#define PCI_DEVICE_ID_ATI_SB900_SATA 0x7800
|
||||
#define PCI_DEVICE_ID_ATI_SB900_SATA_AHCI 0x7801
|
||||
#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID 0x7802
|
||||
#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID5 0x7803
|
||||
#define PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI 0x7804
|
||||
#define PCI_DEVICE_ID_ATI_SB900_IDE 0x780C
|
||||
#define PCI_DEVICE_ID_ATI_SB900_HDA 0x780D
|
||||
#define PCI_DEVICE_ID_ATI_SB900_PCI 0x780F
|
||||
#define PCI_DEVICE_ID_ATI_SB900_PCIEA 0x43A0
|
||||
#define PCI_DEVICE_ID_ATI_SB900_PCIEB 0x43A1
|
||||
#define PCI_DEVICE_ID_ATI_SB900_PCIEC 0x43A2
|
||||
#define PCI_DEVICE_ID_ATI_SB900_PCIED 0x43A3
|
||||
#define PCI_DEVICE_ID_ATI_SB900_SM 0x780B
|
||||
#define PCI_DEVICE_ID_ATI_SB900_USB_16_0 0x7812
|
||||
#define PCI_DEVICE_ID_ATI_SB900_USB_16_1 0x7812
|
||||
#define PCI_DEVICE_ID_ATI_SB900_USB_18_0 0x7807
|
||||
#define PCI_DEVICE_ID_ATI_SB900_USB_18_2 0x7808
|
||||
#define PCI_DEVICE_ID_ATI_SB900_USB_19_0 0x7807
|
||||
#define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808
|
||||
#define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809
|
||||
#define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806
|
||||
|
||||
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910
|
||||
#define PCI_DEVICE_ID_ATI_RS740_HT 0x7911
|
||||
#define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
# Copyright (C) 2010-2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
|
|
|
@ -31,5 +31,3 @@ ramstage-y += PlatformGnbPcie.c
|
|||
|
||||
ramstage-y += reset.c
|
||||
ramstage-y += pmio.c
|
||||
|
||||
subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
|
||||
|
|
|
@ -5,4 +5,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
|
|||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
|
||||
|
||||
subdirs-$(CONFIG_AMD_AGESA) += agesa
|
||||
subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa/f14
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += ../../vendorcode/amd/agesa/f12
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += ../../vendorcode/amd/agesa/f14
|
||||
|
|
|
@ -17,5 +17,6 @@
|
|||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
source src/northbridge/amd/agesa/family12/Kconfig
|
||||
source src/northbridge/amd/agesa/family14/Kconfig
|
||||
|
||||
|
|
|
@ -16,4 +16,5 @@
|
|||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
|
||||
|
|
|
@ -0,0 +1,79 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2009 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
config NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
bool
|
||||
select HAVE_DEBUG_RAM_SETUP
|
||||
select HAVE_DEBUG_SMBUS
|
||||
select HYPERTRANSPORT_PLUGIN_SUPPORT
|
||||
select MMCONF_SUPPORT
|
||||
select NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX
|
||||
|
||||
config HT3_SUPPORT
|
||||
bool
|
||||
default y
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
|
||||
config HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
bool
|
||||
default n
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
|
||||
config MMCONF_BASE_ADDRESS
|
||||
hex
|
||||
default 0xe0000000
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
|
||||
config MMCONF_BUS_NUMBER
|
||||
int
|
||||
default 256
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
|
||||
config DIMM_DDR3
|
||||
bool
|
||||
default n
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
|
||||
config DIMM_REGISTERED
|
||||
bool
|
||||
default n
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
||||
|
||||
if !DIMM_REGISTERED
|
||||
config DIMM_SUPPORT
|
||||
hex
|
||||
default 0x0004
|
||||
endif
|
||||
|
||||
if DIMM_DDR3
|
||||
if DIMM_REGISTERED
|
||||
config DIMM_SUPPORT
|
||||
hex
|
||||
default 0x0005
|
||||
endif
|
||||
endif
|
||||
|
||||
config BOOTBLOCK_NORTHBRIDGE_INIT
|
||||
string
|
||||
default "northbridge/amd/agesa/family12/bootblock.c"
|
||||
depends on NORTHBRIDGE_AMD_AGESA_FAMILY12
|
|
@ -0,0 +1,22 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
driver-y += northbridge.c
|
||||
|
||||
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
|
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* No includes in this file because it is included into northbridge.c.
|
||||
*/
|
||||
|
||||
struct dram_base_mask_t {
|
||||
u32 base; //[47:27] at [28:8]
|
||||
u32 mask; //[47:27] at [28:8] and enable at bit 0
|
||||
};
|
||||
|
||||
static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
|
||||
{
|
||||
device_t dev;
|
||||
struct dram_base_mask_t d;
|
||||
#if defined(__PRE_RAM__)
|
||||
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
|
||||
#else
|
||||
dev = __f1_dev[0];
|
||||
#endif // defined(__PRE_RAM__)
|
||||
|
||||
u32 temp;
|
||||
temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16]
|
||||
d.mask = (temp & 0xffff0000); // mask out DramMask [26:24] too
|
||||
|
||||
temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16]
|
||||
d.mask |= (temp & 1); // read enable bit
|
||||
|
||||
d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too
|
||||
|
||||
return d;
|
||||
}
|
||||
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest,
|
||||
u32 busn_min, u32 busn_max,
|
||||
u32 type)
|
||||
{
|
||||
device_t dev;
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
u32 index_min, index_max;
|
||||
u32 dest_min, dest_max;
|
||||
index_min = busn_min>>2; dest_min = busn_min - (index_min<<2);
|
||||
index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
|
||||
|
||||
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
|
||||
#if defined(__PRE_RAM__)
|
||||
dev = NODE_PCI(nodeid, 1);
|
||||
#else
|
||||
dev = __f1_dev[nodeid];
|
||||
#endif // defined(__PRE_RAM__)
|
||||
if(index_min== index_max) {
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=dest_min; i<=dest_max; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
} else if(index_min<index_max) {
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=dest_min; i<=3; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_min | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
|
||||
pci_write_config32(dev, 0x110, index_max | (type<<28));
|
||||
tempreg = pci_read_config32(dev, 0x114);
|
||||
for(i=0; i<=dest_max; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
pci_write_config32(dev, 0x110, index_max | (type<<28)); // do i need to write it again
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
if((index_max-index_min)>1) {
|
||||
tempreg = 0;
|
||||
for(i=0; i<=3; i++) {
|
||||
tempreg &= ~(0xff<<(i*8));
|
||||
tempreg |= (cfg_map_dest<<(i*8));
|
||||
}
|
||||
for(i=index_min+1; i<index_max;i++) {
|
||||
pci_write_config32(dev, 0x110, i | (type<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
|
||||
#if defined(__PRE_RAM__)
|
||||
static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 io_min, u32 io_max, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
u32 tempreg;
|
||||
device_t dev;
|
||||
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(ht_c_index<4) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
|
||||
for(i=0; i<nodes; i++) {
|
||||
dev = NODE_PCI(i, 1);
|
||||
pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
|
||||
}
|
||||
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
|
||||
for(i=0; i<nodes; i++){
|
||||
dev = NODE_PCI(i, 1);
|
||||
pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
|
||||
}
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
|
||||
if(io_min>io_max) return;
|
||||
|
||||
// for nodeid at first
|
||||
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
|
||||
|
||||
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
|
||||
|
||||
// all other nodes
|
||||
cfg_map_dest = (1<<7) | (0<<6) | (nodeid<<0);
|
||||
for(j = 0; j< nodes; j++) {
|
||||
if(j== nodeid) continue;
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
|
||||
}
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
}
|
||||
|
||||
|
||||
static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
|
||||
u32 io_min, u32 io_max, u32 nodes)
|
||||
{
|
||||
u32 i;
|
||||
device_t dev;
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(ht_c_index<4) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
for(i=0; i<nodes; i++) {
|
||||
dev = NODE_PCI(i, 1);
|
||||
pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0);
|
||||
pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0);
|
||||
}
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
// : if hc_c_index > 3, We should use io_min, io_max to clear extend space
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
|
||||
|
||||
// all nodes
|
||||
cfg_map_dest = 0;
|
||||
for(j = 0; j< nodes; j++) {
|
||||
set_addr_map_reg_4_6_in_one_node(j,cfg_map_dest, io_min, io_max, 4);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif // defined(__PRE_RAM__)
|
||||
|
||||
#if !defined(__PRE_RAM__)
|
||||
static u32 get_io_addr_index(u32 nodeid, u32 linkn)
|
||||
{
|
||||
#if 0
|
||||
u32 index;
|
||||
|
||||
for(index=0; index<256; index++) {
|
||||
if((sysconf.conf_io_addrx[index+4] == 0)){
|
||||
sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ;
|
||||
sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4);
|
||||
return index;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
|
||||
{
|
||||
#if 0
|
||||
u32 index;
|
||||
|
||||
for(index=0; index<64; index++) {
|
||||
if((sysconf.conf_mmio_addrx[index+8] == 0)){
|
||||
sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ;
|
||||
sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4);
|
||||
return index;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
|
||||
u32 io_min, u32 io_max)
|
||||
{
|
||||
|
||||
u32 tempreg;
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
|
||||
pci_write_config32(__f1_dev[0], reg+4, tempreg);
|
||||
|
||||
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
|
||||
#if 0
|
||||
// FIXME: can we use VGA reg instead?
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
|
||||
__func__, dev_path(dev), link);
|
||||
tempreg |= PCI_IO_BASE_VGA_EN;
|
||||
}
|
||||
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
|
||||
tempreg |= PCI_IO_BASE_NO_ISA;
|
||||
}
|
||||
#endif
|
||||
pci_write_config32(__f1_dev[0], reg, tempreg);
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
u32 cfg_map_dest;
|
||||
u32 j;
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
if(io_min>io_max) return;
|
||||
// for nodeid at first
|
||||
cfg_map_dest = (1<<7) | (1<<6) | (linkn<<0);
|
||||
|
||||
set_addr_map_reg_4_6_in_one_node(nodeid, cfg_map_dest, io_min, io_max, 4);
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
}
|
||||
|
||||
|
||||
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
|
||||
{
|
||||
|
||||
u32 tempreg;
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
if(reg!=0x110) {
|
||||
#endif
|
||||
/* io range allocation */
|
||||
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
|
||||
pci_write_config32(__f1_dev[0], reg+4, tempreg);
|
||||
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
|
||||
pci_write_config32(__f1_dev[0], reg, tempreg);
|
||||
#if CONFIG_EXT_CONF_SUPPORT
|
||||
return;
|
||||
}
|
||||
|
||||
device_t dev;
|
||||
u32 j;
|
||||
// if ht_c_index > 3, We should use extend space
|
||||
// for nodeid at first
|
||||
u32 enable;
|
||||
|
||||
if(mmio_min>mmio_max) {
|
||||
return;
|
||||
}
|
||||
|
||||
enable = 1;
|
||||
|
||||
dev = __f1_dev[nodeid];
|
||||
tempreg = ((mmio_min>>3) & 0x1fffff00)| (1<<6) | (linkn<<0);
|
||||
pci_write_config32(dev, 0x110, index | (2<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
|
||||
tempreg = ((mmio_max>>3) & 0x1fffff00) | enable;
|
||||
pci_write_config32(dev, 0x110, index | (3<<28));
|
||||
pci_write_config32(dev, 0x114, tempreg);
|
||||
#endif // CONFIG_EXT_CONF_SUPPORT
|
||||
}
|
||||
|
||||
#endif // !defined(__PRE_RAM__)
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <device/pci_def.h>
|
||||
|
||||
static void bootblock_northbridge_init(void) {
|
||||
}
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_agesa_family12_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_agesa_family12_ops;
|
|
@ -0,0 +1,917 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/hypertransport.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <bitops.h>
|
||||
#include <cpu/cpu.h>
|
||||
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
#include "agesawrapper.h"
|
||||
|
||||
//#define FX_DEVS NODE_NUMS
|
||||
#define FX_DEVS 1
|
||||
|
||||
static device_t __f0_dev[FX_DEVS];
|
||||
static device_t __f1_dev[FX_DEVS];
|
||||
static device_t __f2_dev[FX_DEVS];
|
||||
static device_t __f4_dev[FX_DEVS];
|
||||
static unsigned fx_devs=0;
|
||||
|
||||
|
||||
device_t get_node_pci(u32 nodeid, u32 fn)
|
||||
{
|
||||
return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
|
||||
}
|
||||
|
||||
|
||||
static void get_fx_devs(void)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < FX_DEVS; i++) {
|
||||
__f0_dev[i] = get_node_pci(i, 0);
|
||||
__f1_dev[i] = get_node_pci(i, 1);
|
||||
__f2_dev[i] = get_node_pci(i, 2);
|
||||
__f4_dev[i] = get_node_pci(i, 4);
|
||||
if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
|
||||
fx_devs = i+1;
|
||||
}
|
||||
if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
|
||||
die("Cannot find 0:0x18.[0|1]\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static u32 f1_read_config32(unsigned reg)
|
||||
{
|
||||
if (fx_devs == 0)
|
||||
get_fx_devs();
|
||||
return pci_read_config32(__f1_dev[0], reg);
|
||||
}
|
||||
|
||||
|
||||
static void f1_write_config32(unsigned reg, u32 value)
|
||||
{
|
||||
int i;
|
||||
if (fx_devs == 0)
|
||||
get_fx_devs();
|
||||
for(i = 0; i < fx_devs; i++) {
|
||||
device_t dev;
|
||||
dev = __f1_dev[i];
|
||||
if (dev && dev->enabled) {
|
||||
pci_write_config32(dev, reg, value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static u32 amdfam12_nodeid(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - amdfam12_nodeid\n");
|
||||
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
|
||||
}
|
||||
|
||||
|
||||
#include "amdfam12_conf.c"
|
||||
|
||||
|
||||
static void northbridge_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Northbridge init\n");
|
||||
}
|
||||
|
||||
|
||||
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_vga_enable_reg - Start.\n");
|
||||
val = 1 | (nodeid<<4) | (linkn<<12);
|
||||
/* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
|
||||
0x3c0:0x3df */
|
||||
f1_write_config32(0xf4, val);
|
||||
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - set_vga_enable_reg - End.\n");
|
||||
}
|
||||
|
||||
|
||||
static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
|
||||
unsigned goal_link)
|
||||
{
|
||||
struct resource *res;
|
||||
unsigned nodeid, link = 0;
|
||||
int result;
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - reg_useable - Start.\n");
|
||||
res = 0;
|
||||
for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
|
||||
device_t dev;
|
||||
dev = __f0_dev[nodeid];
|
||||
if (!dev)
|
||||
continue;
|
||||
for(link = 0; !res && (link < 8); link++) {
|
||||
res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
|
||||
}
|
||||
}
|
||||
result = 2;
|
||||
if (res) {
|
||||
result = 0;
|
||||
if ( (goal_link == (link - 1)) &&
|
||||
(goal_nodeid == (nodeid - 1)) &&
|
||||
(res->flags <= 1)) {
|
||||
result = 1;
|
||||
}
|
||||
}
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - reg_useable - End.\n");
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsigned link)
|
||||
{
|
||||
struct resource *resource;
|
||||
u32 result, reg;
|
||||
resource = 0;
|
||||
reg = 0;
|
||||
result = reg_useable(0xc0, dev, nodeid, link);
|
||||
if (result >= 1) {
|
||||
/* I have been allocated this one */
|
||||
reg = 0xc0;
|
||||
}
|
||||
|
||||
//Ext conf space
|
||||
if(!reg) {
|
||||
//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
|
||||
u32 index = get_io_addr_index(nodeid, link);
|
||||
reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
|
||||
}
|
||||
|
||||
resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
|
||||
|
||||
return resource;
|
||||
}
|
||||
|
||||
static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link)
|
||||
{
|
||||
struct resource *resource;
|
||||
u32 free_reg, reg;
|
||||
resource = 0;
|
||||
free_reg = 0;
|
||||
for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
|
||||
int result;
|
||||
result = reg_useable(reg, dev, nodeid, link);
|
||||
if (result == 1) {
|
||||
/* I have been allocated this one */
|
||||
break;
|
||||
}
|
||||
else if (result > 1) {
|
||||
/* I have a free register pair */
|
||||
free_reg = reg;
|
||||
}
|
||||
}
|
||||
if (reg > 0xb8) {
|
||||
reg = free_reg;
|
||||
}
|
||||
|
||||
//Ext conf space
|
||||
if(!reg) {
|
||||
//because of Extend conf space, we will never run out of reg,
|
||||
// but we need one index to differ them. so same node and
|
||||
// same link can have multi range
|
||||
u32 index = get_mmio_addr_index(nodeid, link);
|
||||
reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
|
||||
|
||||
}
|
||||
resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
|
||||
return resource;
|
||||
}
|
||||
|
||||
|
||||
static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - amdfam12_link_read_bases - Start.\n");
|
||||
/* Initialize the io space constraints on the current bus */
|
||||
resource = amdfam12_find_iopair(dev, nodeid, link);
|
||||
if (resource) {
|
||||
u32 align;
|
||||
#if CONFIG_EXT_CONF_SUPPORT == 1
|
||||
if((resource->index & 0x1fff) == 0x1110) { // ext
|
||||
align = 8;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
align = log2(HT_IO_HOST_ALIGN);
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = align;
|
||||
resource->gran = align;
|
||||
resource->limit = 0xffffUL;
|
||||
resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
|
||||
}
|
||||
|
||||
/* Initialize the prefetchable memory constraints on the current bus */
|
||||
resource = amdfam12_find_mempair(dev, nodeid, link);
|
||||
if (resource) {
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = log2(HT_MEM_HOST_ALIGN);
|
||||
resource->gran = log2(HT_MEM_HOST_ALIGN);
|
||||
resource->limit = 0xffffffffffULL;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
||||
resource->flags |= IORESOURCE_BRIDGE;
|
||||
|
||||
#if CONFIG_EXT_CONF_SUPPORT == 1
|
||||
if((resource->index & 0x1fff) == 0x1110) { // ext
|
||||
normalize_resource(resource);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* Initialize the memory constraints on the current bus */
|
||||
resource = amdfam12_find_mempair(dev, nodeid, link);
|
||||
if (resource) {
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = log2(HT_MEM_HOST_ALIGN);
|
||||
resource->gran = log2(HT_MEM_HOST_ALIGN);
|
||||
resource->limit = 0xffffffffffULL;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
|
||||
#if CONFIG_EXT_CONF_SUPPORT == 1
|
||||
if((resource->index & 0x1fff) == 0x1110) { // ext
|
||||
normalize_resource(resource);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - amdfam12_link_read_bases - End.\n");
|
||||
}
|
||||
|
||||
static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
|
||||
{
|
||||
struct resource *min;
|
||||
min = 0;
|
||||
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
|
||||
if (min && tolm > min->base) {
|
||||
tolm = min->base;
|
||||
}
|
||||
return tolm;
|
||||
}
|
||||
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
|
||||
struct hw_mem_hole_info {
|
||||
unsigned hole_startk;
|
||||
int node_id;
|
||||
};
|
||||
|
||||
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
|
||||
{
|
||||
struct hw_mem_hole_info mem_hole;
|
||||
int i;
|
||||
|
||||
mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
|
||||
mem_hole.node_id = -1;
|
||||
|
||||
struct dram_base_mask_t d;
|
||||
u32 hole;
|
||||
d = get_dram_base_mask(0);
|
||||
if(d.mask & 1) {
|
||||
hole = pci_read_config32(__f1_dev[0], 0xf0);
|
||||
if(hole & 1) { // we find the hole
|
||||
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
|
||||
mem_hole.node_id = 0; // record the node No with hole
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
// We need to double check if there is speical set on base reg and limit reg
|
||||
// are not continous instead of hole, it will find out it's hole_startk
|
||||
if(mem_hole.node_id==-1) {
|
||||
resource_t limitk_pri = 0;
|
||||
struct dram_base_mask_t d;
|
||||
resource_t base_k, limit_k;
|
||||
d = get_dram_base_mask(0);
|
||||
if(d.base & 1) {
|
||||
base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
|
||||
if(base_k <= 4 *1024 * 1024) {
|
||||
if(limitk_pri != base_k) { // we find the hole
|
||||
mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
|
||||
mem_hole.node_id = 0;
|
||||
}
|
||||
}
|
||||
|
||||
limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
|
||||
limitk_pri = limit_k;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return mem_hole;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_WRITE_HIGH_TABLES==1
|
||||
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
|
||||
extern uint64_t high_tables_base, high_tables_size;
|
||||
#endif
|
||||
|
||||
#if CONFIG_GFXUMA == 1
|
||||
extern uint64_t uma_memory_base, uma_memory_size;
|
||||
|
||||
static void add_uma_resource(struct device *dev, int index)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - add_uma_resource - Start.\n");
|
||||
|
||||
resource = new_resource(dev, index);
|
||||
resource->base = (resource_t) uma_memory_base;
|
||||
resource->size = (resource_t) uma_memory_size;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
|
||||
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - add_uma_resource - End.\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static void read_resources(device_t dev)
|
||||
{
|
||||
u32 nodeid;
|
||||
struct bus *link;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - read_resources - Start.\n");
|
||||
|
||||
nodeid = amdfam12_nodeid(dev);
|
||||
for(link = dev->link_list; link; link = link->next) {
|
||||
if (link->children) {
|
||||
amdfam12_link_read_bases(dev, nodeid, link->link_num);
|
||||
}
|
||||
}
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - read_resources - End.\n");
|
||||
}
|
||||
|
||||
|
||||
static void set_resource(device_t dev, struct resource *resource,
|
||||
u32 nodeid)
|
||||
{
|
||||
resource_t rbase, rend;
|
||||
unsigned reg, link_num;
|
||||
char buf[50];
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resource - Start.\n");
|
||||
|
||||
/* Make certain the resource has actually been set */
|
||||
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* If I have already stored this resource don't worry about it */
|
||||
if (resource->flags & IORESOURCE_STORED) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Only handle PCI memory and IO resources */
|
||||
if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
|
||||
return;
|
||||
|
||||
/* Ensure I am actually looking at a resource of function 1 */
|
||||
if ((resource->index & 0xffff) < 0x1000) {
|
||||
return;
|
||||
}
|
||||
/* Get the base address */
|
||||
rbase = resource->base;
|
||||
|
||||
/* Get the limit (rounded up) */
|
||||
rend = resource_end(resource);
|
||||
|
||||
/* Get the register and link */
|
||||
reg = resource->index & 0xfff; // 4k
|
||||
link_num = IOINDEX_LINK(resource->index);
|
||||
|
||||
if (resource->flags & IORESOURCE_IO) {
|
||||
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
|
||||
}
|
||||
else if (resource->flags & IORESOURCE_MEM) {
|
||||
set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8]
|
||||
}
|
||||
resource->flags |= IORESOURCE_STORED;
|
||||
sprintf(buf, " <node %x link %x>",
|
||||
nodeid, link_num);
|
||||
report_resource_stored(dev, resource, buf);
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - set_resource - End.\n");
|
||||
}
|
||||
|
||||
|
||||
#if CONFIG_CONSOLE_VGA_MULTI == 1
|
||||
extern device_t vga_pri; // the primary vga device, defined in device.c
|
||||
#endif
|
||||
|
||||
static void create_vga_resource(device_t dev, unsigned nodeid)
|
||||
{
|
||||
struct bus *link;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - create_vga_resource - Start.\n");
|
||||
|
||||
/* find out which link the VGA card is connected,
|
||||
* we only deal with the 'first' vga card */
|
||||
for (link = dev->link_list; link; link = link->next) {
|
||||
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
#if CONFIG_CONSOLE_VGA_MULTI == 1
|
||||
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
|
||||
link->secondary,link->subordinate);
|
||||
/* We need to make sure the vga_pri is under the link */
|
||||
if((vga_pri->bus->secondary >= link->secondary ) &&
|
||||
(vga_pri->bus->secondary <= link->subordinate )
|
||||
)
|
||||
#endif
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* no VGA card installed */
|
||||
if (link == NULL)
|
||||
return;
|
||||
|
||||
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
|
||||
set_vga_enable_reg(nodeid, link->link_num);
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - create_vga_resource - End.\n");
|
||||
}
|
||||
|
||||
|
||||
static void set_resources(device_t dev)
|
||||
{
|
||||
unsigned nodeid;
|
||||
struct bus *bus;
|
||||
struct resource *res;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resources - Start.\n");
|
||||
|
||||
/* Find the nodeid */
|
||||
nodeid = amdfam12_nodeid(dev);
|
||||
|
||||
create_vga_resource(dev, nodeid);
|
||||
|
||||
/* Set each resource we have found */
|
||||
for(res = dev->resource_list; res; res = res->next) {
|
||||
set_resource(dev, res, nodeid);
|
||||
}
|
||||
|
||||
for(bus = dev->link_list; bus; bus = bus->next) {
|
||||
if (bus->children) {
|
||||
assign_resources(bus);
|
||||
}
|
||||
}
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - set_resources - End.\n");
|
||||
}
|
||||
|
||||
|
||||
/* Domain/Root Complex related code */
|
||||
|
||||
static void domain_read_resources(device_t dev)
|
||||
{
|
||||
unsigned reg;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_read_resources - Start.\n");
|
||||
|
||||
/* Find the already assigned resource pairs */
|
||||
get_fx_devs();
|
||||
for(reg = 0x80; reg <= 0xc0; reg+= 0x08) {
|
||||
u32 base, limit;
|
||||
base = f1_read_config32(reg);
|
||||
limit = f1_read_config32(reg + 0x04);
|
||||
/* Is this register allocated? */
|
||||
if ((base & 3) != 0) {
|
||||
unsigned nodeid, reg_link;
|
||||
device_t reg_dev;
|
||||
if(reg<0xc0) { // mmio
|
||||
nodeid = (limit & 0xf) + (base&0x30);
|
||||
} else { // io
|
||||
nodeid = (limit & 0xf) + ((base>>4)&0x30);
|
||||
}
|
||||
reg_link = (limit >> 4) & 7;
|
||||
reg_dev = __f0_dev[nodeid];
|
||||
if (reg_dev) {
|
||||
/* Reserve the resource */
|
||||
struct resource *res;
|
||||
res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
|
||||
if (res) {
|
||||
res->flags = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/* FIXME: do we need to check extend conf space?
|
||||
I don't believe that much preset value */
|
||||
|
||||
#if CONFIG_PCI_64BIT_PREF_MEM == 0
|
||||
//- pci_domain_read_resources(dev);
|
||||
|
||||
struct resource *resource;
|
||||
/* Initialize the system-wide I/O space constraints. */
|
||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
||||
resource->base = 0x1000;
|
||||
resource->limit = 0xffffUL;
|
||||
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED;
|
||||
|
||||
/* Initialize the system-wide memory resources constraints. */
|
||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||
resource->base = 0xc0000000ULL;
|
||||
resource->limit = 0xdfffffffULL;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED;
|
||||
#else
|
||||
struct bus *link;
|
||||
struct resource *resource;
|
||||
for(link=dev->link_list; link; link = link->next) {
|
||||
/* Initialize the system wide io space constraints */
|
||||
resource = new_resource(dev, 0|(link->link_num<<2));
|
||||
resource->base = 0x400;
|
||||
resource->limit = 0xffffUL;
|
||||
resource->flags = IORESOURCE_IO;
|
||||
|
||||
/* Initialize the system wide prefetchable memory resources constraints */
|
||||
resource = new_resource(dev, 1|(link->link_num<<2));
|
||||
resource->limit = 0xfcffffffffULL;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
||||
|
||||
/* Initialize the system wide memory resources constraints */
|
||||
resource = new_resource(dev, 2|(link->link_num<<2));
|
||||
resource->limit = 0xfcffffffffULL;
|
||||
resource->flags = IORESOURCE_MEM;
|
||||
}
|
||||
#endif
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_read_resources - End.\n");
|
||||
}
|
||||
|
||||
|
||||
static void domain_set_resources(device_t dev)
|
||||
{
|
||||
u32 val;
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_set_resources - Start.\n");
|
||||
printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev);
|
||||
|
||||
|
||||
#if CONFIG_PCI_64BIT_PREF_MEM == 1
|
||||
struct resource *io, *mem1, *mem2;
|
||||
struct resource *res;
|
||||
#endif
|
||||
unsigned long mmio_basek;
|
||||
u32 pci_tolm;
|
||||
int i, idx;
|
||||
struct bus *link;
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
struct hw_mem_hole_info mem_hole;
|
||||
u32 reset_memhole = 1;
|
||||
#endif
|
||||
|
||||
#if CONFIG_PCI_64BIT_PREF_MEM == 1
|
||||
|
||||
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
|
||||
for(link = dev->link_list; link; link = link->next) {
|
||||
/* Now reallocate the pci resources memory with the
|
||||
* highest addresses I can manage.
|
||||
*/
|
||||
mem1 = find_resource(dev, 1|(link->link_num<<2));
|
||||
mem2 = find_resource(dev, 2|(link->link_num<<2));
|
||||
|
||||
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
|
||||
mem1->base, mem1->limit, mem1->size, mem1->align);
|
||||
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
|
||||
mem2->base, mem2->limit, mem2->size, mem2->align);
|
||||
|
||||
/* See if both resources have roughly the same limits */
|
||||
if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
|
||||
((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
|
||||
{
|
||||
/* If so place the one with the most stringent alignment first
|
||||
*/
|
||||
if (mem2->align > mem1->align) {
|
||||
struct resource *tmp;
|
||||
tmp = mem1;
|
||||
mem1 = mem2;
|
||||
mem2 = tmp;
|
||||
}
|
||||
/* Now place the memory as high up as it will go */
|
||||
mem2->base = resource_max(mem2);
|
||||
mem1->limit = mem2->base - 1;
|
||||
mem1->base = resource_max(mem1);
|
||||
}
|
||||
else {
|
||||
/* Place the resources as high up as they will go */
|
||||
mem2->base = resource_max(mem2);
|
||||
mem1->base = resource_max(mem1);
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
|
||||
mem1->base, mem1->limit, mem1->size, mem1->align);
|
||||
printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
|
||||
mem2->base, mem2->limit, mem2->size, mem2->align);
|
||||
}
|
||||
|
||||
for(res = &dev->resource_list; res; res = res->next)
|
||||
{
|
||||
res->flags |= IORESOURCE_ASSIGNED;
|
||||
res->flags |= IORESOURCE_STORED;
|
||||
report_resource_stored(dev, res, "");
|
||||
}
|
||||
#endif
|
||||
|
||||
pci_tolm = 0xffffffffUL;
|
||||
for(link = dev->link_list; link; link = link->next) {
|
||||
pci_tolm = my_find_pci_tolm(link, pci_tolm);
|
||||
}
|
||||
|
||||
// FIXME handle interleaved nodes. If you fix this here, please fix
|
||||
// amdk8, too.
|
||||
mmio_basek = pci_tolm >> 10;
|
||||
/* Round mmio_basek to something the processor can support */
|
||||
mmio_basek &= ~((1 << 6) -1);
|
||||
|
||||
// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
|
||||
// MMIO hole. If you fix this here, please fix amdk8, too.
|
||||
/* Round the mmio hole to 64M */
|
||||
mmio_basek &= ~((64*1024) - 1);
|
||||
|
||||
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
|
||||
/* if the hw mem hole is already set in raminit stage, here we will compare
|
||||
* mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
|
||||
* use hole_basek as mmio_basek and we don't need to reset hole.
|
||||
* otherwise We reset the hole to the mmio_basek
|
||||
*/
|
||||
|
||||
mem_hole = get_hw_mem_hole_info();
|
||||
|
||||
// Use hole_basek as mmio_basek, and we don't need to reset hole anymore
|
||||
if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
|
||||
mmio_basek = mem_hole.hole_startk;
|
||||
reset_memhole = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
idx = 0x10;
|
||||
|
||||
struct dram_base_mask_t d;
|
||||
resource_t basek, limitk, sizek; // 4 1T
|
||||
|
||||
d = get_dram_base_mask(0);
|
||||
|
||||
if (d.mask & 1) {
|
||||
basek = ((resource_t)(d.base)) << 8;
|
||||
limitk = (resource_t)((d.mask << 8) | 0xFFFFFF);
|
||||
printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
|
||||
|
||||
/* Convert these values to multiples of 1K for ease of math. */
|
||||
basek >>= 10;
|
||||
limitk >>= 10;
|
||||
sizek = limitk - basek + 1;
|
||||
|
||||
printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
|
||||
|
||||
/* see if we need a hole from 0xa0000 to 0xbffff */
|
||||
if ((basek < 640) && (sizek > 768)) {
|
||||
printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
|
||||
ram_resource(dev, (idx | 0), basek, 640 - basek);
|
||||
idx += 0x10;
|
||||
basek = 768;
|
||||
sizek = limitk - 768;
|
||||
}
|
||||
|
||||
|
||||
printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_basek, basek, limitk);
|
||||
|
||||
/* split the region to accomodate pci memory space */
|
||||
if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
|
||||
if (basek <= mmio_basek) {
|
||||
unsigned pre_sizek;
|
||||
pre_sizek = mmio_basek - basek;
|
||||
if(pre_sizek>0) {
|
||||
ram_resource(dev, idx, basek, pre_sizek);
|
||||
idx += 0x10;
|
||||
sizek -= pre_sizek;
|
||||
#if CONFIG_WRITE_HIGH_TABLES==1
|
||||
if (high_tables_base==0) {
|
||||
/* Leave some space for ACPI, PIRQ and MP tables */
|
||||
#if CONFIG_GFXUMA == 1
|
||||
high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
|
||||
#else
|
||||
high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
|
||||
#endif
|
||||
high_tables_size = HIGH_TABLES_SIZE * 1024;
|
||||
printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
|
||||
high_tables_base);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
basek = mmio_basek;
|
||||
}
|
||||
if ((basek + sizek) <= 4*1024*1024) {
|
||||
sizek = 0;
|
||||
}
|
||||
else {
|
||||
basek = 4*1024*1024;
|
||||
sizek -= (4*1024*1024 - mmio_basek);
|
||||
}
|
||||
}
|
||||
|
||||
ram_resource(dev, (idx | 0), basek, sizek);
|
||||
idx += 0x10;
|
||||
#if CONFIG_WRITE_HIGH_TABLES==1
|
||||
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
|
||||
0, mmio_basek, basek, limitk);
|
||||
if (high_tables_base==0) {
|
||||
/* Leave some space for ACPI, PIRQ and MP tables */
|
||||
#if CONFIG_GFXUMA == 1
|
||||
high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
|
||||
printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base);
|
||||
#else
|
||||
high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
|
||||
#endif
|
||||
high_tables_size = HIGH_TABLES_SIZE * 1024;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek);
|
||||
printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size);
|
||||
|
||||
#if CONFIG_GFXUMA == 1
|
||||
printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
|
||||
add_uma_resource(dev, 7);
|
||||
#endif
|
||||
|
||||
for(link = dev->link_list; link; link = link->next) {
|
||||
if (link->children) {
|
||||
assign_resources(link);
|
||||
}
|
||||
}
|
||||
printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_set_resources - End.\n");
|
||||
}
|
||||
|
||||
|
||||
static void domain_enable_resources(device_t dev)
|
||||
{
|
||||
// u32 val;
|
||||
/* Must be called after PCI enumeration and resource allocation */
|
||||
// printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - Start.\n");
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - Start.\n");
|
||||
// val = agesawrapper_amdinitmid ();
|
||||
// if(val) {
|
||||
// printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
|
||||
// }
|
||||
// printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - End.\n");
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_enable_resources - End.\n");
|
||||
}
|
||||
|
||||
|
||||
/* Bus related code */
|
||||
|
||||
|
||||
static void cpu_bus_read_resources(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_read_resources - Start.\n");
|
||||
|
||||
#if CONFIG_MMCONF_SUPPORT
|
||||
struct resource *resource = new_resource(dev, 0xc0010058);
|
||||
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
|
||||
resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
|
||||
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||
#endif
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_read_resources - End.\n");
|
||||
}
|
||||
|
||||
static void cpu_bus_set_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource = find_resource(dev, 0xc0010058);
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_set_resources - Start.\n");
|
||||
if (resource) {
|
||||
report_resource_stored(dev, resource, " <mmconfig>");
|
||||
}
|
||||
pci_dev_set_resources(dev);
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_set_resources - End.\n");
|
||||
}
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - Start.\n");
|
||||
initialize_cpus(dev->link_list);
|
||||
|
||||
#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
|
||||
/* Must be called after PCI enumeration and resource allocation */
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - Start.\n");
|
||||
sb_After_Pci_Init ();
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - End.\n");
|
||||
#endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
|
||||
|
||||
#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
|
||||
/* Must be called after PCI enumeration and resource allocation */
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - Start.\n");
|
||||
sb_Mid_Post_Init ();
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - End.\n");
|
||||
#endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
|
||||
|
||||
/* Must be called after PCI enumeration and resource allocation */
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - Start.\n");
|
||||
val = agesawrapper_amdinitmid ();
|
||||
if(val) {
|
||||
printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
|
||||
}
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - End.\n");
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - End.\n");
|
||||
}
|
||||
|
||||
|
||||
/* North Bridge Structures */
|
||||
|
||||
static struct device_operations northbridge_operations = {
|
||||
.read_resources = read_resources,
|
||||
.set_resources = set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = northbridge_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
|
||||
static const struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &northbridge_operations,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x1705,
|
||||
};
|
||||
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_family12_ops = {
|
||||
CHIP_NAME("AMD Family 12h Northbridge")
|
||||
.enable_dev = 0,
|
||||
};
|
||||
|
||||
|
||||
/* Root Complex Structures */
|
||||
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = domain_read_resources,
|
||||
.set_resources = domain_set_resources,
|
||||
.enable_resources = domain_enable_resources,
|
||||
.init = NULL,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = cpu_bus_read_resources,
|
||||
.set_resources = cpu_bus_set_resources,
|
||||
.enable_resources = NULL,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
|
||||
static void root_complex_enable_dev(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - root_complex_enable_dev - Start.\n");
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
printk(BIOS_DEBUG, "Fam12h - northbridge.c - root_complex_enable_dev - End.\n");
|
||||
}
|
||||
|
||||
|
||||
struct chip_operations northbridge_amd_agesa_family12_root_complex_ops = {
|
||||
CHIP_NAME("AMD Family 12h Root Complex")
|
||||
.enable_dev = root_complex_enable_dev,
|
||||
};
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef NORTHBRIDGE_AMD_AGESA_FAM12H_H
|
||||
#define NORTHBRIDGE_AMD_AGESA_FAM12H_H
|
||||
|
||||
static struct device_operations pci_domain_ops;
|
||||
static struct device_operations cpu_bus_ops;
|
||||
|
||||
#endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */
|
|
@ -0,0 +1,2 @@
|
|||
config NORTHBRIDGE_AMD_AGESA_FAMILY12_ROOT_COMPLEX
|
||||
bool
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
struct northbridge_amd_agesa_family12_root_complex_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_agesa_family12_root_complex_ops;
|
|
@ -0,0 +1,346 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file
|
||||
*/
|
||||
|
||||
DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM12H", "AMD-ACPI", 0x1000)
|
||||
{
|
||||
/*
|
||||
* These objects were referenced but not defined in this table
|
||||
*/
|
||||
External (\_SB_.PCI0, DeviceObj)
|
||||
|
||||
Scope (\_SB.PCI0)
|
||||
{
|
||||
Name (BUSN, Package (0x20) /* HC_NUMS */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x10101010,
|
||||
0x11111111,
|
||||
0x12121212,
|
||||
0x13131313,
|
||||
0x14141414,
|
||||
0x15151515,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc
|
||||
})
|
||||
Name (MMIO, Package (0x80) /* HC_NUMS * 4 */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888
|
||||
})
|
||||
Name (PCIO, Package (0x40) /* HC_NUMS * 2 */
|
||||
{
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0xaaaaaaaa,
|
||||
0xbbbbbbbb,
|
||||
0xcccccccc,
|
||||
0xdddddddd,
|
||||
0xeeeeeeee,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x99999999,
|
||||
0xaaaaaaaa,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444
|
||||
})
|
||||
Name (SBLK, 0x11)
|
||||
Name (TOM1, 0xaaaaaaaa)
|
||||
Name (SBDN, 0xbbbbbbbb)
|
||||
Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888
|
||||
})
|
||||
Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */
|
||||
{
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888,
|
||||
0x11111111,
|
||||
0x22222222,
|
||||
0x33333333,
|
||||
0x44444444,
|
||||
0x55555555,
|
||||
0x66666666,
|
||||
0x77777777,
|
||||
0x88888888
|
||||
})
|
||||
Name (CBB, 0x99)
|
||||
Name (CBST, 0x88)
|
||||
Name (CBB2, 0x77)
|
||||
Name (CBS2, 0x66)
|
||||
|
||||
}
|
||||
}
|
||||
|
|
@ -13,4 +13,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
|
|||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
|
||||
subdirs-$(CONFIG_AMD_CIMX_SB800) += cimx
|
||||
subdirs-$(CONFIG_AMD_CIMX_SB900) += cimx
|
||||
|
||||
|
|
|
@ -18,3 +18,4 @@
|
|||
#
|
||||
|
||||
source src/southbridge/amd/cimx/sb800/Kconfig
|
||||
source src/southbridge/amd/cimx/sb900/Kconfig
|
||||
|
|
|
@ -17,3 +17,4 @@
|
|||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
|
||||
|
|
|
@ -0,0 +1,384 @@
|
|||
/*****************************************************************************
|
||||
* AMD Generic Encapsulated Software Architecture */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* Agesa structures and definitions
|
||||
*
|
||||
* Contains AMD AGESA/CIMx core interface
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: Include
|
||||
* @e \$Revision:$ @e \$Date:$
|
||||
*/
|
||||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _AMD_H_
|
||||
#define _AMD_H_
|
||||
|
||||
// AGESA Types and Definitions
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#define LAST_ENTRY 0xFFFFFFFF
|
||||
#define IOCF8 0xCF8
|
||||
#define IOCFC 0xCFC
|
||||
#define IN
|
||||
#define OUT
|
||||
|
||||
#ifndef Int16FromChar
|
||||
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
|
||||
#endif
|
||||
#ifndef Int32FromChar
|
||||
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
|
||||
#endif
|
||||
|
||||
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
|
||||
|
||||
typedef unsigned int AGESA_STATUS;
|
||||
|
||||
#define AGESA_SUCCESS ((AGESA_STATUS) 0x0)
|
||||
#define AGESA_ALERT ((AGESA_STATUS) 0x40000000)
|
||||
#define AGESA_WARNING ((AGESA_STATUS) 0x40000001)
|
||||
#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003)
|
||||
#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001)
|
||||
#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)
|
||||
#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
|
||||
|
||||
typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
|
||||
typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
|
||||
typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
|
||||
|
||||
///This allocation type is used by the AmdCreateStruct entry point
|
||||
typedef enum {
|
||||
PreMemHeap = 0, ///< Create heap in cache.
|
||||
PostMemDram, ///< Create heap in memory.
|
||||
ByHost ///< Create heap by Host.
|
||||
} ALLOCATION_METHOD;
|
||||
|
||||
/// These width descriptors are used by the library function, and others, to specify the data size
|
||||
typedef enum ACCESS_WIDTH {
|
||||
AccessWidth8 = 1, ///< Access width is 8 bits.
|
||||
AccessWidth16, ///< Access width is 16 bits.
|
||||
AccessWidth32, ///< Access width is 32 bits.
|
||||
AccessWidth64, ///< Access width is 64 bits.
|
||||
|
||||
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
|
||||
AccessS3SaveWidth16, ///< Save 16 bits data.
|
||||
AccessS3SaveWidth32, ///< Save 32 bits data.
|
||||
AccessS3SaveWidth64, ///< Save 64 bits data.
|
||||
} ACCESS_WIDTH;
|
||||
|
||||
// AGESA Structures
|
||||
|
||||
/// The standard header for all AGESA services.
|
||||
typedef struct _AMD_CONFIG_PARAMS {
|
||||
IN unsigned int ImageBasePtr; ///< The AGESA Image base address.
|
||||
IN unsigned int Func; ///< The service desired, @sa dispatch.h.
|
||||
IN unsigned int AltImageBasePtr; ///< Alternate Image location
|
||||
IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured.
|
||||
union { ///< Callback pointer
|
||||
IN unsigned long long PlaceHolder; ///< Place holder
|
||||
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
|
||||
} CALLBACK;
|
||||
IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use.
|
||||
} AMD_CONFIG_PARAMS;
|
||||
|
||||
|
||||
/// AGESA Binary module header structure
|
||||
typedef struct _AMD_IMAGE_HEADER {
|
||||
IN unsigned int Signature; ///< Binary Signature
|
||||
IN signed char CreatorID[8]; ///< 8 characters ID
|
||||
IN signed char Version[12]; ///< 12 characters version
|
||||
IN unsigned int ModuleInfoOffset; ///< Offset of module
|
||||
IN unsigned int EntryPointAddress; ///< Entry address
|
||||
IN unsigned int ImageBase; ///< Image base
|
||||
IN unsigned int RelocTableOffset; ///< Relocate Table offset
|
||||
IN unsigned int ImageSize; ///< Size
|
||||
IN unsigned short Checksum; ///< Checksum
|
||||
IN unsigned char ImageType; ///< Type
|
||||
IN unsigned char V_Reserved; ///< Reserved
|
||||
} AMD_IMAGE_HEADER;
|
||||
|
||||
/// AGESA Binary module header structure
|
||||
typedef struct _AMD_MODULE_HEADER {
|
||||
IN unsigned int ModuleHeaderSignature; ///< Module signature
|
||||
IN signed char ModuleIdentifier[8]; ///< 8 characters ID
|
||||
IN signed char ModuleVersion[12]; ///< 12 characters version
|
||||
IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher
|
||||
IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link
|
||||
} AMD_MODULE_HEADER;
|
||||
|
||||
#define FUNC_0 0 // bit-placed for PCI address creation
|
||||
#define FUNC_1 1
|
||||
#define FUNC_2 2
|
||||
#define FUNC_3 3
|
||||
#define FUNC_4 4
|
||||
#define FUNC_5 5
|
||||
#define FUNC_6 6
|
||||
#define FUNC_7 7
|
||||
|
||||
// SBDFO - Segment Bus Device Function Offset
|
||||
// 31:28 Segment (4-bits)
|
||||
// 27:20 Bus (8-bits)
|
||||
// 19:15 Device (5-bits)
|
||||
// 14:12 Function (3-bits)
|
||||
// 11:00 Offset (12-bits)
|
||||
|
||||
#if 0
|
||||
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
|
||||
(((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
|
||||
#endif
|
||||
#define ILLEGAL_SBDFO 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
/// CPUID data received registers format
|
||||
typedef struct _SB_CPUID_DATA {
|
||||
IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX
|
||||
IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX
|
||||
IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX
|
||||
IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX
|
||||
} SB_CPUID_DATA;
|
||||
*/
|
||||
|
||||
#define WARM_RESET 1
|
||||
#define COLD_RESET 2 // Cold reset
|
||||
#define RESET_CPU 4 // Triggers a CPU reset
|
||||
|
||||
/// HT frequency for external callbacks
|
||||
typedef enum {
|
||||
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
|
||||
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
|
||||
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
|
||||
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
|
||||
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
|
||||
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
|
||||
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
|
||||
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
|
||||
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
|
||||
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
|
||||
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
|
||||
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
|
||||
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
|
||||
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
|
||||
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
|
||||
HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks
|
||||
} HT_FREQUENCIES;
|
||||
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x0000000000000001ull
|
||||
#endif
|
||||
#ifndef BIT1
|
||||
#define BIT1 0x0000000000000002ull
|
||||
#endif
|
||||
#ifndef BIT2
|
||||
#define BIT2 0x0000000000000004ull
|
||||
#endif
|
||||
#ifndef BIT3
|
||||
#define BIT3 0x0000000000000008ull
|
||||
#endif
|
||||
#ifndef BIT4
|
||||
#define BIT4 0x0000000000000010ull
|
||||
#endif
|
||||
#ifndef BIT5
|
||||
#define BIT5 0x0000000000000020ull
|
||||
#endif
|
||||
#ifndef BIT6
|
||||
#define BIT6 0x0000000000000040ull
|
||||
#endif
|
||||
#ifndef BIT7
|
||||
#define BIT7 0x0000000000000080ull
|
||||
#endif
|
||||
#ifndef BIT8
|
||||
#define BIT8 0x0000000000000100ull
|
||||
#endif
|
||||
#ifndef BIT9
|
||||
#define BIT9 0x0000000000000200ull
|
||||
#endif
|
||||
#ifndef BIT10
|
||||
#define BIT10 0x0000000000000400ull
|
||||
#endif
|
||||
#ifndef BIT11
|
||||
#define BIT11 0x0000000000000800ull
|
||||
#endif
|
||||
#ifndef BIT12
|
||||
#define BIT12 0x0000000000001000ull
|
||||
#endif
|
||||
#ifndef BIT13
|
||||
#define BIT13 0x0000000000002000ull
|
||||
#endif
|
||||
#ifndef BIT14
|
||||
#define BIT14 0x0000000000004000ull
|
||||
#endif
|
||||
#ifndef BIT15
|
||||
#define BIT15 0x0000000000008000ull
|
||||
#endif
|
||||
#ifndef BIT16
|
||||
#define BIT16 0x0000000000010000ull
|
||||
#endif
|
||||
#ifndef BIT17
|
||||
#define BIT17 0x0000000000020000ull
|
||||
#endif
|
||||
#ifndef BIT18
|
||||
#define BIT18 0x0000000000040000ull
|
||||
#endif
|
||||
#ifndef BIT19
|
||||
#define BIT19 0x0000000000080000ull
|
||||
#endif
|
||||
#ifndef BIT20
|
||||
#define BIT20 0x0000000000100000ull
|
||||
#endif
|
||||
#ifndef BIT21
|
||||
#define BIT21 0x0000000000200000ull
|
||||
#endif
|
||||
#ifndef BIT22
|
||||
#define BIT22 0x0000000000400000ull
|
||||
#endif
|
||||
#ifndef BIT23
|
||||
#define BIT23 0x0000000000800000ull
|
||||
#endif
|
||||
#ifndef BIT24
|
||||
#define BIT24 0x0000000001000000ull
|
||||
#endif
|
||||
#ifndef BIT25
|
||||
#define BIT25 0x0000000002000000ull
|
||||
#endif
|
||||
#ifndef BIT26
|
||||
#define BIT26 0x0000000004000000ull
|
||||
#endif
|
||||
#ifndef BIT27
|
||||
#define BIT27 0x0000000008000000ull
|
||||
#endif
|
||||
#ifndef BIT28
|
||||
#define BIT28 0x0000000010000000ull
|
||||
#endif
|
||||
#ifndef BIT29
|
||||
#define BIT29 0x0000000020000000ull
|
||||
#endif
|
||||
#ifndef BIT30
|
||||
#define BIT30 0x0000000040000000ull
|
||||
#endif
|
||||
#ifndef BIT31
|
||||
#define BIT31 0x0000000080000000ull
|
||||
#endif
|
||||
#ifndef BIT32
|
||||
#define BIT32 0x0000000100000000ull
|
||||
#endif
|
||||
#ifndef BIT33
|
||||
#define BIT33 0x0000000200000000ull
|
||||
#endif
|
||||
#ifndef BIT34
|
||||
#define BIT34 0x0000000400000000ull
|
||||
#endif
|
||||
#ifndef BIT35
|
||||
#define BIT35 0x0000000800000000ull
|
||||
#endif
|
||||
#ifndef BIT36
|
||||
#define BIT36 0x0000001000000000ull
|
||||
#endif
|
||||
#ifndef BIT37
|
||||
#define BIT37 0x0000002000000000ull
|
||||
#endif
|
||||
#ifndef BIT38
|
||||
#define BIT38 0x0000004000000000ull
|
||||
#endif
|
||||
#ifndef BIT39
|
||||
#define BIT39 0x0000008000000000ull
|
||||
#endif
|
||||
#ifndef BIT40
|
||||
#define BIT40 0x0000010000000000ull
|
||||
#endif
|
||||
#ifndef BIT41
|
||||
#define BIT41 0x0000020000000000ull
|
||||
#endif
|
||||
#ifndef BIT42
|
||||
#define BIT42 0x0000040000000000ull
|
||||
#endif
|
||||
#ifndef BIT43
|
||||
#define BIT43 0x0000080000000000ull
|
||||
#endif
|
||||
#ifndef BIT44
|
||||
#define BIT44 0x0000100000000000ull
|
||||
#endif
|
||||
#ifndef BIT45
|
||||
#define BIT45 0x0000200000000000ull
|
||||
#endif
|
||||
#ifndef BIT46
|
||||
#define BIT46 0x0000400000000000ull
|
||||
#endif
|
||||
#ifndef BIT47
|
||||
#define BIT47 0x0000800000000000ull
|
||||
#endif
|
||||
#ifndef BIT48
|
||||
#define BIT48 0x0001000000000000ull
|
||||
#endif
|
||||
#ifndef BIT49
|
||||
#define BIT49 0x0002000000000000ull
|
||||
#endif
|
||||
#ifndef BIT50
|
||||
#define BIT50 0x0004000000000000ull
|
||||
#endif
|
||||
#ifndef BIT51
|
||||
#define BIT51 0x0008000000000000ull
|
||||
#endif
|
||||
#ifndef BIT52
|
||||
#define BIT52 0x0010000000000000ull
|
||||
#endif
|
||||
#ifndef BIT53
|
||||
#define BIT53 0x0020000000000000ull
|
||||
#endif
|
||||
#ifndef BIT54
|
||||
#define BIT54 0x0040000000000000ull
|
||||
#endif
|
||||
#ifndef BIT55
|
||||
#define BIT55 0x0080000000000000ull
|
||||
#endif
|
||||
#ifndef BIT56
|
||||
#define BIT56 0x0100000000000000ull
|
||||
#endif
|
||||
#ifndef BIT57
|
||||
#define BIT57 0x0200000000000000ull
|
||||
#endif
|
||||
#ifndef BIT58
|
||||
#define BIT58 0x0400000000000000ull
|
||||
#endif
|
||||
#ifndef BIT59
|
||||
#define BIT59 0x0800000000000000ull
|
||||
#endif
|
||||
#ifndef BIT60
|
||||
#define BIT60 0x1000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT61
|
||||
#define BIT61 0x2000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT62
|
||||
#define BIT62 0x4000000000000000ull
|
||||
#endif
|
||||
#ifndef BIT63
|
||||
#define BIT63 0x8000000000000000ull
|
||||
#endif
|
||||
#endif
|
|
@ -0,0 +1,175 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _AMD_SB_LIB_H_
|
||||
#define _AMD_SB_LIB_H_
|
||||
|
||||
typedef signed char *va_list;
|
||||
#ifndef _INTSIZEOF
|
||||
#define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )
|
||||
#endif
|
||||
|
||||
// Also support coding convention rules for var arg macros
|
||||
#ifndef va_start
|
||||
#define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) )
|
||||
#endif
|
||||
#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
|
||||
#define va_end(ap) ( ap = (va_list)0 )
|
||||
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
#define IMAGE_ALIGN 32*1024
|
||||
#define NUM_IMAGE_LOCATION 32
|
||||
|
||||
//Entry Point Call
|
||||
typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
|
||||
|
||||
//Hook Call
|
||||
|
||||
typedef struct _CIMFILEHEADER
|
||||
{
|
||||
unsigned int AMDLogo;
|
||||
unsigned long long CreatorID;
|
||||
unsigned int Version1;
|
||||
unsigned int Version2;
|
||||
unsigned int Version3;
|
||||
unsigned int ModuleInfoOffset;
|
||||
unsigned int EntryPoint;
|
||||
unsigned int ImageBase;
|
||||
unsigned int RelocTableOffset;
|
||||
unsigned int ImageSize;
|
||||
unsigned short CheckSum;
|
||||
unsigned char ImageType;
|
||||
unsigned char Reserved2;
|
||||
} CIMFILEHEADER;
|
||||
|
||||
#ifndef BIT0
|
||||
#define BIT0 (1 << 0)
|
||||
#endif
|
||||
#ifndef BIT1
|
||||
#define BIT1 (1 << 1)
|
||||
#endif
|
||||
#ifndef BIT2
|
||||
#define BIT2 (1 << 2)
|
||||
#endif
|
||||
#ifndef BIT3
|
||||
#define BIT3 (1 << 3)
|
||||
#endif
|
||||
#ifndef BIT4
|
||||
#define BIT4 (1 << 4)
|
||||
#endif
|
||||
#ifndef BIT5
|
||||
#define BIT5 (1 << 5)
|
||||
#endif
|
||||
#ifndef BIT6
|
||||
#define BIT6 (1 << 6)
|
||||
#endif
|
||||
#ifndef BIT7
|
||||
#define BIT7 (1 << 7)
|
||||
#endif
|
||||
#ifndef BIT8
|
||||
#define BIT8 (1 << 8)
|
||||
#endif
|
||||
#ifndef BIT9
|
||||
#define BIT9 (1 << 9)
|
||||
#endif
|
||||
#ifndef BIT10
|
||||
#define BIT10 (1 << 10)
|
||||
#endif
|
||||
#ifndef BIT11
|
||||
#define BIT11 (1 << 11)
|
||||
#endif
|
||||
#ifndef BIT12
|
||||
#define BIT12 (1 << 12)
|
||||
#endif
|
||||
#ifndef BIT13
|
||||
#define BIT13 (1 << 13)
|
||||
#endif
|
||||
#ifndef BIT14
|
||||
#define BIT14 (1 << 14)
|
||||
#endif
|
||||
#ifndef BIT15
|
||||
#define BIT15 (1 << 15)
|
||||
#endif
|
||||
#ifndef BIT16
|
||||
#define BIT16 (1 << 16)
|
||||
#endif
|
||||
#ifndef BIT17
|
||||
#define BIT17 (1 << 17)
|
||||
#endif
|
||||
#ifndef BIT18
|
||||
#define BIT18 (1 << 18)
|
||||
#endif
|
||||
#ifndef BIT19
|
||||
#define BIT19 (1 << 19)
|
||||
#endif
|
||||
#ifndef BIT20
|
||||
#define BIT20 (1 << 20)
|
||||
#endif
|
||||
#ifndef BIT21
|
||||
#define BIT21 (1 << 21)
|
||||
#endif
|
||||
#ifndef BIT22
|
||||
#define BIT22 (1 << 22)
|
||||
#endif
|
||||
#ifndef BIT23
|
||||
#define BIT23 (1 << 23)
|
||||
#endif
|
||||
#ifndef BIT24
|
||||
#define BIT24 (1 << 24)
|
||||
#endif
|
||||
#ifndef BIT25
|
||||
#define BIT25 (1 << 25)
|
||||
#endif
|
||||
#ifndef BIT26
|
||||
#define BIT26 (1 << 26)
|
||||
#endif
|
||||
#ifndef BIT27
|
||||
#define BIT27 (1 << 27)
|
||||
#endif
|
||||
#ifndef BIT28
|
||||
#define BIT28 (1 << 28)
|
||||
#endif
|
||||
#ifndef BIT29
|
||||
#define BIT29 (1 << 29)
|
||||
#endif
|
||||
#ifndef BIT30
|
||||
#define BIT30 (1 << 30)
|
||||
#endif
|
||||
#ifndef BIT31
|
||||
#define BIT31 (1 << 31)
|
||||
#endif
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AccWidthUint8 = 0,
|
||||
AccWidthUint16,
|
||||
AccWidthUint32,
|
||||
} ACC_WIDTH;
|
||||
|
||||
#define S3_SAVE 0x80
|
||||
|
||||
#endif
|
|
@ -0,0 +1,54 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
config SOUTHBRIDGE_AMD_CIMX_SB900
|
||||
bool
|
||||
select IOAPIC
|
||||
|
||||
if SOUTHBRIDGE_AMD_CIMX_SB900
|
||||
config SATA_CONTROLLER_MODE
|
||||
hex
|
||||
default 0x0
|
||||
help
|
||||
0x0 = Native IDE mode.
|
||||
0x1 = RAID mode.
|
||||
0x2 = AHCI mode.
|
||||
0x3 = Legacy IDE mode.
|
||||
0x4 = IDE->AHCI mode.
|
||||
0x5 = AHCI mode as 7804 ID (AMD driver).
|
||||
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
|
||||
|
||||
config PCIB_ENABLE
|
||||
bool
|
||||
default n
|
||||
help
|
||||
n = Disable PCI Bridge Device 14 Function 4.
|
||||
y = Enable PCI Bridge Device 14 Function 4.
|
||||
|
||||
config ACPI_SCI_IRQ
|
||||
hex
|
||||
default 0x9
|
||||
help
|
||||
Set SCI IRQ to 9.
|
||||
|
||||
config BOOTBLOCK_SOUTHBRIDGE_INIT
|
||||
string
|
||||
default "southbridge/amd/cimx/sb900/bootblock.c"
|
||||
endif #SOUTHBRIDGE_AMD_CIMX_SB900
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
subdirs-$(CONFIG_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900
|
||||
|
||||
# SB900 Platform Files
|
||||
|
||||
romstage-y += early.c
|
||||
romstage-y += smbus.c
|
||||
|
||||
ramstage-y += late.c
|
||||
ramstage-y += early.c
|
||||
|
||||
driver-y += smbus.c
|
||||
driver-y += lpc.c
|
||||
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CIMX_SB_EARLY_H_
|
||||
#define _CIMX_SB_EARLY_H_
|
||||
|
||||
#define PM_INDEX 0xcd6
|
||||
#define PM_DATA 0xcd7
|
||||
|
||||
#define SB900_ACPI_IO_BASE 0x800
|
||||
|
||||
#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */
|
||||
#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */
|
||||
#define ACPI_PMA_CNT_BLK (SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */
|
||||
#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */
|
||||
#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */
|
||||
#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */
|
||||
|
||||
#define REV_SB900_A11 0x11
|
||||
#define REV_SB900_A12 0x12
|
||||
|
||||
/**
|
||||
* @brief Get SouthBridge device number, called by finalize_node_setup()
|
||||
* @param[in] bus target bus number
|
||||
* @return southbridge device number
|
||||
*/
|
||||
u32 get_sbdn(u32 bus);
|
||||
|
||||
/**
|
||||
* South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
|
||||
*/
|
||||
void sb_poweron_init(void);
|
||||
void sb_before_pci_init(void);
|
||||
|
||||
void sb_After_Pci_Init (void);
|
||||
void sb_Mid_Post_Init (void);
|
||||
void sb_Late_Post (void);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _AMD_SBPLATFORM_H_
|
||||
#define _AMD_SBPLATFORM_H_
|
||||
|
||||
//#include "cbtypes.h"
|
||||
#ifdef NULL
|
||||
#undef NULL
|
||||
#endif
|
||||
#define NULL 0
|
||||
|
||||
typedef unsigned long long PLACEHOLDER;
|
||||
|
||||
#ifndef SBOEM_ACPI_RESTORE_SWSMI
|
||||
#define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
|
||||
#define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
|
||||
#endif
|
||||
|
||||
#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
|
||||
|
||||
/*
|
||||
/// Extended PCI Address
|
||||
typedef struct _EXT_PCI_ADDR {
|
||||
UINT32 Reg :16; ///< / PCI Register
|
||||
UINT32 Func:3; ///< / PCI Function
|
||||
UINT32 Dev :5; ///< / PCI Device
|
||||
UINT32 Bus :8; ///< / PCI Address
|
||||
} EXT_PCI_ADDR;
|
||||
|
||||
/// PCI Address
|
||||
typedef union _PCI_ADDR {
|
||||
UINT32 ADDR; ///< / 32 bit Address
|
||||
EXT_PCI_ADDR Addr; ///< / Extended PCI Address
|
||||
} PCI_ADDR;
|
||||
*/
|
||||
#endif
|
||||
#define FIXUP_PTR(ptr) ptr
|
||||
|
||||
#include "AmdSbLib.h"
|
||||
#include "Amd.h"
|
||||
#include "Hudson-2.h"
|
||||
#include "SbType.h"
|
||||
#include "AcpiLib.h"
|
||||
#include "SbDef.h"
|
||||
#include "AmdSbLib.h"
|
||||
#include "SbSubFun.h"
|
||||
#include "Oem.h"
|
||||
#include "AMD.h"
|
||||
#include "SbBiosRamUsage.h"
|
||||
#include "EcFan.h"
|
||||
|
||||
//------------------------------------------------------------------------------------------------------------------------//
|
||||
/**
|
||||
* SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
|
||||
* SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
|
||||
* HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
|
||||
* IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
|
||||
* SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
|
||||
* NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
|
||||
* SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
|
||||
* SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
|
||||
* SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
|
||||
* SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
|
||||
* SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
|
||||
* SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
* FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
|
||||
*/
|
||||
#define SB_CIMx_PARAMETER 0x02
|
||||
|
||||
// Generic
|
||||
#define cimSpreadSpectrumDefault TRUE
|
||||
#define cimSpreadSpectrumTypeDefault 0x00 // Normal
|
||||
#define cimHpetTimerDefault TRUE
|
||||
#define cimHpetMsiDisDefault FALSE // Enable
|
||||
#define cimIrConfigDefault 0x00 // Disable
|
||||
#define cimSpiFastReadEnableDefault 0x00 // Disable
|
||||
#define cimSpiFastReadSpeedDefault 0x00 // NULL
|
||||
// GPP/AB Controller
|
||||
#define cimNbSbGen2Default TRUE
|
||||
#define cimAlinkPhyPllPowerDownDefault TRUE
|
||||
#define cimResetCpuOnSyncFloodDefault TRUE
|
||||
#define cimGppGen2Default FALSE
|
||||
#define cimGppMemWrImproveDefault TRUE
|
||||
#define cimGppPortAspmDefault FALSE
|
||||
#define cimGppLaneReversalDefault FALSE
|
||||
#define cimGppPhyPllPowerDownDefault TRUE
|
||||
// USB Controller
|
||||
#define cimUsbPhyPowerDownDefault FALSE
|
||||
// GEC Controller
|
||||
#define cimSBGecDebugBusDefault FALSE
|
||||
#define cimSBGecPwrDefault 0x03
|
||||
// Sata Controller
|
||||
#define cimSataSetMaxGen2Default 0x00
|
||||
#define cimSATARefClkSelDefault 0x10
|
||||
#define cimSATARefDivSelDefault 0x80
|
||||
#define cimSataAggrLinkPmCapDefault TRUE
|
||||
#define cimSataPortMultCapDefault TRUE
|
||||
#define cimSataPscCapDefault 0x00 // Enable
|
||||
#define cimSataSscCapDefault 0x00 // Enable
|
||||
#define cimSataFisBasedSwitchingDefault FALSE
|
||||
#define cimSataCccSupportDefault FALSE
|
||||
#define cimSataClkAutoOffDefault FALSE
|
||||
#define cimNativepciesupportDefault FALSE
|
||||
// Fusion Related
|
||||
#define cimAcDcMsgDefault FALSE
|
||||
#define cimTimerTickTrackDefault FALSE
|
||||
#define cimClockInterruptTagDefault FALSE
|
||||
#define cimOhciTrafficHandingDefault FALSE
|
||||
#define cimEhciTrafficHandingDefault FALSE
|
||||
#define cimFusionMsgCMultiCoreDefault FALSE
|
||||
#define cimFusionMsgCStageDefault FALSE
|
||||
#endif // _AMD_SBPLATFORM_H_
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <arch/romcc_io.h>
|
||||
|
||||
|
||||
#if CONFIG_CONSOLE_POST == 1
|
||||
|
||||
/* Data */
|
||||
#define UART_RBR 0x00
|
||||
#define UART_TBR 0x00
|
||||
|
||||
/* Control */
|
||||
#define UART_IER 0x01
|
||||
#define UART_IIR 0x02
|
||||
#define UART_FCR 0x02
|
||||
#define UART_LCR 0x03
|
||||
#define UART_MCR 0x04
|
||||
#define UART_DLL 0x00
|
||||
#define UART_DLM 0x01
|
||||
|
||||
/* Status */
|
||||
#define UART_LSR 0x05
|
||||
#define UART_MSR 0x06
|
||||
#define UART_SCR 0x07
|
||||
|
||||
#ifndef CONFIG_TTYS0_DIV
|
||||
#if ((115200%CONFIG_TTYS0_BAUD) != 0)
|
||||
#error Bad ttys0 baud rate
|
||||
#endif
|
||||
#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
|
||||
#endif // CONFIG_TTYS0_DIV
|
||||
|
||||
#define UART_LCS CONFIG_TTYS0_LCS
|
||||
|
||||
#endif // CONFIG_CONSOLE_POST == 1
|
||||
|
||||
|
||||
static void sb900_enable_rom(void)
|
||||
{
|
||||
u32 word;
|
||||
u32 dword;
|
||||
device_t dev;
|
||||
|
||||
dev = PCI_DEV(0, 0x14, 0x03);
|
||||
/* SB900 LPC Bridge 0:20:3:44h.
|
||||
* BIT6: Port Enable for serial port 0x3f8-0x3ff
|
||||
* BIT29: Port Enable for KBC port 0x60 and 0x64
|
||||
* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
|
||||
*/
|
||||
dword = pci_io_read_config32(dev, 0x44);
|
||||
//dword |= (1<<6) | (1<<29) | (1<<30) ;
|
||||
/*Turn on all of LPC IO Port decode enable */
|
||||
dword = 0xffffffff;
|
||||
pci_io_write_config32(dev, 0x44, dword);
|
||||
|
||||
/* SB900 LPC Bridge 0:20:3:48h.
|
||||
* BIT0: Port Enable for SuperIO 0x2E-0x2F
|
||||
* BIT1: Port Enable for SuperIO 0x4E-0x4F
|
||||
* BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
|
||||
* BIT6: Port Enable for RTC IO 0x70-0x73
|
||||
* BIT21: Port Enable for Port 0x80
|
||||
*/
|
||||
dword = pci_io_read_config32(dev, 0x48);
|
||||
dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
|
||||
pci_io_write_config32(dev, 0x48, dword);
|
||||
|
||||
/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
|
||||
/* Set the 4MB enable bits */
|
||||
word = pci_io_read_config16(dev, 0x6c);
|
||||
word = 0xFFC0;
|
||||
pci_io_write_config16(dev, 0x6c, word);
|
||||
}
|
||||
|
||||
static void bootblock_southbridge_init(void)
|
||||
{
|
||||
/* Setup the rom access for 2M */
|
||||
sb900_enable_rom();
|
||||
}
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CBTYPES_H_
|
||||
#define _CBTYPES_H_
|
||||
|
||||
//#include <stdint.h>
|
||||
|
||||
typedef signed long long __int64;
|
||||
typedef void VOID;
|
||||
typedef unsigned int UINTN;
|
||||
typedef signed char CHAR8;
|
||||
typedef unsigned char UINT8;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned int UINT32;
|
||||
typedef unsigned long long UINT64;
|
||||
typedef unsigned char BOOLEAN;
|
||||
|
||||
#define DMSG_SB_TRACE 0x02
|
||||
#define TRACE(Arguments)
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
#ifndef VOLATILE
|
||||
#define VOLATILE volatile
|
||||
#endif
|
||||
#ifndef CONST
|
||||
#define CONST const
|
||||
#endif
|
||||
|
||||
#ifndef IN
|
||||
#define IN
|
||||
#endif
|
||||
#ifndef OUT
|
||||
#define OUT
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CIMX_SB900_CHIP_H_
|
||||
#define _CIMX_SB900_CHIP_H_
|
||||
|
||||
extern struct chip_operations southbridge_amd_cimx_sb900_ops;
|
||||
|
||||
/*
|
||||
* configuration set in mainboard/devicetree.cb
|
||||
* boot_switch_sata_ide:
|
||||
* 0 -set SATA as primary, PATA(IDE) as secondary.
|
||||
* 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
|
||||
* gpp_configuration - The configuration of General Purpose Port A/B/C/D
|
||||
* 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
|
||||
* 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
|
||||
* 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
|
||||
* 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
|
||||
*/
|
||||
struct southbridge_amd_cimx_sb900_config
|
||||
{
|
||||
u32 boot_switch_sata_ide : 1;
|
||||
u8 gpp_configuration;
|
||||
};
|
||||
|
||||
#endif /* _CIMX_SB900_CHIP_H_ */
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations southbridge_amd_cimx_sb900_ops = {
|
||||
CHIP_NAME("AMD South Bridge SB900")
|
||||
};
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
//#include <config.h>
|
||||
#include <stdint.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h> /* inl, outl */
|
||||
#include <arch/romcc_io.h> /* device_t */
|
||||
#include "SbPlatform.h"
|
||||
#include "SbEarly.h"
|
||||
#include "cfg.h" /*sb900_cimx_config*/
|
||||
#include <console/console.h>
|
||||
#include <console/loglevel.h>
|
||||
#include "smbus.h"
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get SouthBridge device number
|
||||
* @param[in] bus target bus number
|
||||
* @return southbridge device number
|
||||
*/
|
||||
u32 get_sbdn(u32 bus)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - Start.\n");
|
||||
//dev = PCI_DEV(bus, 0x14, 0);
|
||||
dev = pci_locate_device_on_bus(
|
||||
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB900_SM),
|
||||
bus);
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - End.\n");
|
||||
return (dev >> 15) & 0x1f;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief South Bridge CIMx romstage entry,
|
||||
* wrapper of sbPowerOnInit entry point.
|
||||
*/
|
||||
void sb_poweron_init(void)
|
||||
{
|
||||
AMDSBCFG sb_early_cfg;
|
||||
u8 data;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - Start.\n");
|
||||
|
||||
//Enable/Disable PCI Bridge Device 14 Function 4.
|
||||
outb(0xEA, 0xCD6);
|
||||
data = inb(0xCD7);
|
||||
data &= !BIT0;
|
||||
if(!CONFIG_PCIB_ENABLE) {
|
||||
data |= BIT0;
|
||||
}
|
||||
outb(data, 0xCD7);
|
||||
|
||||
SbPowerOnInit_Config(&sb_early_cfg);
|
||||
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
|
||||
//AmdSbDispatcher(&sb_early_cfg);
|
||||
//TODO
|
||||
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
|
||||
// VerifyImage() will fail, LocateImage() take minitues to find the image.
|
||||
sbPowerOnInit(&sb_early_cfg);
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_poweron_init - End.\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief South Bridge CIMx romstage entry,
|
||||
* wrapper of sbPowerOnInit entry point.
|
||||
*/
|
||||
void sb_before_pci_init(void)
|
||||
{
|
||||
AMDSBCFG sb_early_cfg;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - Start.\n");
|
||||
sb900_cimx_config(&sb_early_cfg);
|
||||
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
|
||||
//AmdSbDispatcher(&sb_early_cfg);
|
||||
//TODO
|
||||
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
|
||||
// VerifyImage() will fail, LocateImage() take minitues to find the image.
|
||||
sbBeforePciInit(&sb_early_cfg);
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_before_pci_init - End.\n");
|
||||
}
|
||||
|
||||
void sb_After_Pci_Init(void)
|
||||
{
|
||||
AMDSBCFG sb_early_cfg;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
|
||||
sb900_cimx_config(&sb_early_cfg);
|
||||
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
|
||||
//AmdSbDispatcher(&sb_early_cfg);
|
||||
//TODO
|
||||
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
|
||||
// VerifyImage() will fail, LocateImage() take minitues to find the image.
|
||||
sbAfterPciInit(&sb_early_cfg);
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
|
||||
}
|
||||
|
||||
void sb_Mid_Post_Init(void)
|
||||
{
|
||||
AMDSBCFG sb_early_cfg;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n");
|
||||
sb900_cimx_config(&sb_early_cfg);
|
||||
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
|
||||
//AmdSbDispatcher(&sb_early_cfg);
|
||||
//TODO
|
||||
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
|
||||
// VerifyImage() will fail, LocateImage() take minitues to find the image.
|
||||
sbMidPostInit(&sb_early_cfg);
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_Mid_Post_Init - End.\n");
|
||||
}
|
||||
|
||||
void sb_Late_Post(void)
|
||||
{
|
||||
AMDSBCFG sb_early_cfg;
|
||||
u8 data;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - Start.\n");
|
||||
sb900_cimx_config(&sb_early_cfg);
|
||||
//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
|
||||
//AmdSbDispatcher(&sb_early_cfg);
|
||||
//TODO
|
||||
//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
|
||||
// VerifyImage() will fail, LocateImage() take minitues to find the image.
|
||||
sbLatePost(&sb_early_cfg);
|
||||
|
||||
//Set ACPI SCI IRQ to 0x9.
|
||||
data = CONFIG_ACPI_SCI_IRQ;
|
||||
outb(0x10, 0xC00);
|
||||
outb(data, 0xC01);
|
||||
outb(0x90, 0xC00);
|
||||
outb(data, 0xC01);
|
||||
|
||||
if (data > 0x7) {
|
||||
data = inb(0x4D1);
|
||||
data |= (1 << (CONFIG_ACPI_SCI_IRQ - 8));
|
||||
outb(data, 0x4D1);
|
||||
} else {
|
||||
data = inb(0x4D0);
|
||||
data |= (1 << (CONFIG_ACPI_SCI_IRQ));
|
||||
outb(data, 0x4D0);
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Early.c - sb_Late_Post - End.\n");
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,477 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <device/device.h> /* device_t */
|
||||
#include <device/pci.h> /* device_operations */
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/smbus.h> /* smbus_bus_operations */
|
||||
#include <console/console.h> /* printk */
|
||||
#include "lpc.h" /* lpc_read_resources */
|
||||
#include "SbPlatform.h" /* Platfrom Specific Definitions */
|
||||
#include "cfg.h" /* sb900 Cimx configuration */
|
||||
#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */
|
||||
|
||||
|
||||
/*implement in mainboard.c*/
|
||||
//void set_pcie_assert(void);
|
||||
//void set_pcie_deassert(void);
|
||||
void set_pcie_reset(void);
|
||||
void set_pcie_dereset(void);
|
||||
|
||||
|
||||
#ifndef _RAMSTAGE_
|
||||
#define _RAMSTAGE_
|
||||
#endif
|
||||
static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config
|
||||
static AMDSBCFG *sb_config = &sb_late_cfg;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Entry point of Southbridge CIMx callout
|
||||
*
|
||||
* prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
|
||||
*
|
||||
* @param[in] func Southbridge CIMx Function ID.
|
||||
* @param[in] data Southbridge Input Data.
|
||||
* @param[in] sb_config Southbridge configuration structure pointer.
|
||||
*
|
||||
*/
|
||||
u32 sb900_callout_entry(u32 func, u32 data, void* config)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n");
|
||||
switch (func) {
|
||||
case CB_SBGPP_RESET_ASSERT:
|
||||
//set_pcie_assert();
|
||||
//- set_pcie_reset();
|
||||
break;
|
||||
|
||||
case CB_SBGPP_RESET_DEASSERT:
|
||||
//set_pcie_deassert();
|
||||
//- set_pcie_dereset();
|
||||
break;
|
||||
|
||||
//- case IMC_FIRMWARE_FAIL:
|
||||
//- break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
static struct pci_operations lops_pci = {
|
||||
.set_subsystem = 0,
|
||||
};
|
||||
|
||||
static void lpc_enable_resources(device_t dev)
|
||||
{
|
||||
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n");
|
||||
pci_dev_enable_resources(dev);
|
||||
//lpc_enable_childrens_resources(dev);
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n");
|
||||
}
|
||||
|
||||
static void lpc_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
|
||||
/* SB Configure HPET base and enable bit */
|
||||
//- hpetInit(sb_config, &(sb_config->BuildParameters));
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = lpc_read_resources,
|
||||
.set_resources = lpc_set_resources,
|
||||
.enable_resources = lpc_enable_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = scan_static_bus,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_LPC,
|
||||
};
|
||||
|
||||
|
||||
static void sata_enable_resources(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n");
|
||||
//- sataInitAfterPciEnum(sb_config);
|
||||
pci_dev_enable_resources(dev);
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n");
|
||||
}
|
||||
|
||||
static void sata_init(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n");
|
||||
sb_config->StdHeader.Func = SB_MID_POST_INIT;
|
||||
//- AmdSbDispatcher(sb_config); //sataInitMidPost only
|
||||
//- commonInitLateBoot(sb_config);
|
||||
//- sataInitLatePost(sb_config);
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n");
|
||||
}
|
||||
|
||||
static struct device_operations sata_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = sata_enable_resources, //pci_dev_enable_resources,
|
||||
.init = sata_init,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver sata_driver __pci_driver = {
|
||||
.ops = &sata_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
#if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3)
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_SATA, //SATA IDE Mode
|
||||
#endif
|
||||
#if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4)
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, //SATA AHCI Mode
|
||||
#endif
|
||||
#if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6)
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI, //SATA AMDAHCI Mode
|
||||
#endif
|
||||
#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0)
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID5, //SATA RAID5 Mode
|
||||
#endif
|
||||
#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1)
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_SATA_RAID, //SATA RAID Mode
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
#if CONFIG_USBDEBUG
|
||||
static void usb_set_resources(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
u32 base;
|
||||
u32 old_debug;
|
||||
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - Start.\n");
|
||||
old_debug = get_ehci_debug();
|
||||
set_ehci_debug(0);
|
||||
|
||||
pci_dev_set_resources(dev);
|
||||
|
||||
res = find_resource(dev, 0x10);
|
||||
set_ehci_debug(old_debug);
|
||||
if (!res)
|
||||
return;
|
||||
base = res->base;
|
||||
set_ehci_base(base);
|
||||
report_resource_stored(dev, res, "");
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - usb_set_resources - End.\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
static void usb_init(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n");
|
||||
//- usbInitAfterPciInit(sb_config);
|
||||
//- commonInitLateBoot(sb_config);
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n");
|
||||
}
|
||||
|
||||
static struct device_operations usb_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
#if CONFIG_USBDEBUG
|
||||
.set_resources = usb_set_resources,
|
||||
#else
|
||||
.set_resources = pci_dev_set_resources,
|
||||
#endif
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = usb_init,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
/*
|
||||
* The pci id of usb ctrl 0 and 1 are the same.
|
||||
*/
|
||||
static const struct pci_driver usb_xhci123_driver __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */
|
||||
};
|
||||
|
||||
static const struct pci_driver usb_ohci123_driver __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
|
||||
};
|
||||
|
||||
static const struct pci_driver usb_ehci123_driver __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
|
||||
};
|
||||
|
||||
static const struct pci_driver usb_ohci4_driver __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, /* OHCI-USB4 */
|
||||
};
|
||||
|
||||
|
||||
static void azalia_init(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n");
|
||||
//- azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n");
|
||||
}
|
||||
|
||||
static struct device_operations azalia_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = azalia_init,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver azalia_driver __pci_driver = {
|
||||
.ops = &azalia_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_HDA,
|
||||
};
|
||||
|
||||
|
||||
static void gec_init(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n");
|
||||
//- gecInitAfterPciEnum(sb_config);
|
||||
//- gecInitLatePost(sb_config);
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n");
|
||||
}
|
||||
|
||||
static struct device_operations gec_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = gec_init,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver gec_driver __pci_driver = {
|
||||
.ops = &gec_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_GEC,
|
||||
};
|
||||
|
||||
|
||||
static void pcie_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n");
|
||||
//- sbPcieGppLateInit(sb_config);
|
||||
printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n");
|
||||
}
|
||||
|
||||
static struct device_operations pci_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pci_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver pci_driver __pci_driver = {
|
||||
.ops = &pci_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_PCI,
|
||||
};
|
||||
|
||||
|
||||
struct device_operations bridge_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pci_scan_bridge,
|
||||
.enable = 0,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
/* 0:15:0 PCIe PortA */
|
||||
static const struct pci_driver PORTA_driver __pci_driver = {
|
||||
.ops = &bridge_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
|
||||
};
|
||||
|
||||
/* 0:15:1 PCIe PortB */
|
||||
static const struct pci_driver PORTB_driver __pci_driver = {
|
||||
.ops = &bridge_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
|
||||
};
|
||||
|
||||
/* 0:15:2 PCIe PortC */
|
||||
static const struct pci_driver PORTC_driver __pci_driver = {
|
||||
.ops = &bridge_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
|
||||
};
|
||||
|
||||
/* 0:15:3 PCIe PortD */
|
||||
static const struct pci_driver PORTD_driver __pci_driver = {
|
||||
.ops = &bridge_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_ATI_SB900_PCIED,
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @brief SB Cimx entry point sbBeforePciInit wrapper
|
||||
*/
|
||||
static void sb900_enable(device_t dev)
|
||||
{
|
||||
u8 gpp_port = 0;
|
||||
struct southbridge_amd_cimx_sb900_config *sb_chip =
|
||||
(struct southbridge_amd_cimx_sb900_config *)(dev->chip_info);
|
||||
|
||||
sb900_cimx_config(sb_config);
|
||||
printk(BIOS_DEBUG, "sb900_enable() ");
|
||||
|
||||
/* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
|
||||
//- commonInitEarlyBoot(sb_config);
|
||||
//- commonInitEarlyPost(sb_config);
|
||||
|
||||
switch (dev->path.pci.devfn) {
|
||||
case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */
|
||||
//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
|
||||
break;
|
||||
|
||||
case (0x11 << 3) | 0: /* 0:11.0 SATA */
|
||||
if (dev->enabled) {
|
||||
sb_config->SATAMODE.SataMode.SataController = ENABLED;
|
||||
if (1 == sb_chip->boot_switch_sata_ide)
|
||||
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
|
||||
else if (0 == sb_chip->boot_switch_sata_ide)
|
||||
sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
|
||||
} else {
|
||||
sb_config->SATAMODE.SataMode.SataController = DISABLED;
|
||||
}
|
||||
|
||||
//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
|
||||
break;
|
||||
|
||||
case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
|
||||
case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
|
||||
case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
|
||||
case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
|
||||
case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
|
||||
//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
|
||||
break;
|
||||
|
||||
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
|
||||
break;
|
||||
|
||||
case (0x14 << 3) | 1: /* 0:14:1 IDE */
|
||||
if (dev->enabled) {
|
||||
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
|
||||
} else {
|
||||
sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
|
||||
}
|
||||
//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
|
||||
break;
|
||||
|
||||
case (0x14 << 3) | 2: /* 0:14:2 HDA */
|
||||
if (dev->enabled) {
|
||||
if (AZALIA_DISABLE == sb_config->AzaliaController) {
|
||||
sb_config->AzaliaController = AZALIA_AUTO;
|
||||
}
|
||||
printk(BIOS_DEBUG, "hda enabled\n");
|
||||
} else {
|
||||
sb_config->AzaliaController = AZALIA_DISABLE;
|
||||
printk(BIOS_DEBUG, "hda disabled\n");
|
||||
}
|
||||
//- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
|
||||
break;
|
||||
|
||||
|
||||
case (0x14 << 3) | 3: /* 0:14:3 LPC */
|
||||
break;
|
||||
|
||||
case (0x14 << 3) | 4: /* 0:14:4 PCI */
|
||||
break;
|
||||
|
||||
case (0x14 << 3) | 6: /* 0:14:6 GEC */
|
||||
if (dev->enabled) {
|
||||
sb_config->GecConfig = 0;
|
||||
printk(BIOS_DEBUG, "gec enabled\n");
|
||||
} else {
|
||||
sb_config->GecConfig = 1;
|
||||
printk(BIOS_DEBUG, "gec disabled\n");
|
||||
}
|
||||
//- gecInitBeforePciEnum(sb_config); // Init GEC
|
||||
break;
|
||||
|
||||
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
|
||||
case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
|
||||
case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
|
||||
case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
|
||||
gpp_port = (dev->path.pci.devfn) & 0x03;
|
||||
if (dev->enabled) {
|
||||
sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
|
||||
} else {
|
||||
sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
|
||||
}
|
||||
|
||||
/*
|
||||
* GPP_CFGMODE_X4000: PortA Lanes[3:0]
|
||||
* GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
|
||||
* GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
|
||||
* GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
|
||||
*/
|
||||
if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
|
||||
sb_config->GppLinkConfig = sb_chip->gpp_configuration;
|
||||
}
|
||||
|
||||
//- sbPcieGppEarlyInit(sb_config);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Special setting ABCFG registers before PCI emulation. */
|
||||
//- abSpecialSetBeforePciEnum(sb_config);
|
||||
//- usbDesertPll(sb_config);
|
||||
//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
|
||||
//AmdSbDispatcher(sb_config);
|
||||
}
|
||||
|
||||
struct chip_operations southbridge_amd_cimx_sb900_ops = {
|
||||
CHIP_NAME("ATI SB900")
|
||||
.enable_dev = sb900_enable,
|
||||
};
|
|
@ -0,0 +1,179 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <device/pci.h>
|
||||
#include "lpc.h"
|
||||
#include <console/console.h> /* printk */
|
||||
|
||||
|
||||
void lpc_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - Start.\n");
|
||||
/* Get the normal pci resources of this device */
|
||||
pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
|
||||
|
||||
pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
|
||||
|
||||
/* Add an extra subtractive resource for both memory and I/O. */
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
||||
res->base = 0;
|
||||
res->size = 0x1000;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||
res->base = 0xff800000;
|
||||
res->size = 0x00800000; /* 8 MB for flash */
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, 3); /* IOAPIC */
|
||||
res->base = 0xfec00000;
|
||||
res->size = 0x00001000;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
compact_resources(dev);
|
||||
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - End.\n");
|
||||
}
|
||||
|
||||
void lpc_set_resources(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n");
|
||||
pci_dev_set_resources(dev);
|
||||
|
||||
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
|
||||
res = find_resource(dev, SPIROM_BASE_ADDRESS);
|
||||
pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
|
||||
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable resources for children devices
|
||||
*
|
||||
* @param dev the device whos children's resources are to be enabled
|
||||
*
|
||||
*/
|
||||
void lpc_enable_childrens_resources(device_t dev)
|
||||
{
|
||||
struct bus *link;
|
||||
u32 reg, reg_x;
|
||||
int var_num = 0;
|
||||
u16 reg_var[3];
|
||||
|
||||
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - Start.\n");
|
||||
reg = pci_read_config32(dev, 0x44);
|
||||
reg_x = pci_read_config32(dev, 0x48);
|
||||
|
||||
for (link = dev->link_list; link; link = link->next) {
|
||||
device_t child;
|
||||
for (child = link->children; child;
|
||||
child = child->sibling) {
|
||||
if (child->enabled
|
||||
&& (child->path.type == DEVICE_PATH_PNP)) {
|
||||
struct resource *res;
|
||||
for (res = child->resource_list; res; res = res->next) {
|
||||
u32 base, end; /* don't need long long */
|
||||
if (!(res->flags & IORESOURCE_IO))
|
||||
continue;
|
||||
base = res->base;
|
||||
end = resource_end(res);
|
||||
/*
|
||||
printk(BIOS_DEBUG, "sb900 lpc decode:%s, base=0x%08x, end=0x%08x\n",
|
||||
dev_path(child), base, end);
|
||||
*/
|
||||
switch (base) {
|
||||
case 0x60: /* KB */
|
||||
case 0x64: /* MS */
|
||||
reg |= (1 << 29);
|
||||
break;
|
||||
case 0x3f8: /* COM1 */
|
||||
reg |= (1 << 6);
|
||||
break;
|
||||
case 0x2f8: /* COM2 */
|
||||
reg |= (1 << 7);
|
||||
break;
|
||||
case 0x378: /* Parallal 1 */
|
||||
reg |= (1 << 0);
|
||||
break;
|
||||
case 0x3f0: /* FD0 */
|
||||
reg |= (1 << 26);
|
||||
break;
|
||||
case 0x220: /* Aduio 0 */
|
||||
reg |= (1 << 8);
|
||||
break;
|
||||
case 0x300: /* Midi 0 */
|
||||
reg |= (1 << 18);
|
||||
break;
|
||||
case 0x400:
|
||||
reg_x |= (1 << 16);
|
||||
break;
|
||||
case 0x480:
|
||||
reg_x |= (1 << 17);
|
||||
break;
|
||||
case 0x500:
|
||||
reg_x |= (1 << 18);
|
||||
break;
|
||||
case 0x580:
|
||||
reg_x |= (1 << 19);
|
||||
break;
|
||||
case 0x4700:
|
||||
reg_x |= (1 << 22);
|
||||
break;
|
||||
case 0xfd60:
|
||||
reg_x |= (1 << 23);
|
||||
break;
|
||||
default:
|
||||
if (var_num >= 3)
|
||||
continue; /* only 3 var ; compact them ? */
|
||||
switch (var_num) {
|
||||
case 0:
|
||||
reg_x |= (1 << 2);
|
||||
break;
|
||||
case 1:
|
||||
reg_x |= (1 << 24);
|
||||
break;
|
||||
case 2:
|
||||
reg_x |= (1 << 25);
|
||||
break;
|
||||
}
|
||||
reg_var[var_num++] =
|
||||
base & 0xffff;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
pci_write_config32(dev, 0x44, reg);
|
||||
pci_write_config32(dev, 0x48, reg_x);
|
||||
/* Set WideIO for as many IOs found (fall through is on purpose) */
|
||||
switch (var_num) {
|
||||
case 2:
|
||||
pci_write_config16(dev, 0x90, reg_var[2]);
|
||||
case 1:
|
||||
pci_write_config16(dev, 0x66, reg_var[1]);
|
||||
case 0:
|
||||
//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
|
||||
break;
|
||||
}
|
||||
printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - End.\n");
|
||||
}
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _SB900_LPC_H_
|
||||
#define _SB900_LPC_H_
|
||||
|
||||
|
||||
#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */
|
||||
|
||||
void lpc_read_resources(device_t dev);
|
||||
void lpc_set_resources(device_t dev);
|
||||
void lpc_enable_childrens_resources(device_t dev);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,270 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <arch/io.h>
|
||||
#include "smbus.h"
|
||||
#include <console/console.h> /* printk */
|
||||
|
||||
static inline void smbus_delay(void)
|
||||
{
|
||||
outb(inb(0x80), 0x80);
|
||||
}
|
||||
|
||||
static int smbus_wait_until_ready(u32 smbus_io_base)
|
||||
{
|
||||
u32 loops;
|
||||
|
||||
loops = SMBUS_TIMEOUT;
|
||||
do {
|
||||
u8 val;
|
||||
val = inb(smbus_io_base + SMBHSTSTAT);
|
||||
val &= 0x1f;
|
||||
if (val == 0) { /* ready now */
|
||||
return 0;
|
||||
}
|
||||
outb(val, smbus_io_base + SMBHSTSTAT);
|
||||
} while (--loops);
|
||||
|
||||
return -2; /* time out */
|
||||
}
|
||||
|
||||
static int smbus_wait_until_done(u32 smbus_io_base)
|
||||
{
|
||||
u32 loops;
|
||||
|
||||
loops = SMBUS_TIMEOUT;
|
||||
do {
|
||||
u8 val;
|
||||
|
||||
val = inb(smbus_io_base + SMBHSTSTAT);
|
||||
val &= 0x1f; /* mask off reserved bits */
|
||||
if (val & 0x1c) {
|
||||
return -5; /* error */
|
||||
}
|
||||
if (val == 0x02) {
|
||||
outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
|
||||
return 0;
|
||||
}
|
||||
} while (--loops);
|
||||
|
||||
return -3; /* timeout */
|
||||
}
|
||||
|
||||
int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0) {
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
|
||||
return -2; /* not ready */
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - Start.\n");
|
||||
/* set the device I'm talking too */
|
||||
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
|
||||
|
||||
byte = inb(smbus_io_base + SMBHSTCTRL);
|
||||
byte &= 0xe3; /* Clear [4:2] */
|
||||
byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
|
||||
outb(byte, smbus_io_base + SMBHSTCTRL);
|
||||
|
||||
/* poll for transaction completion */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0) {
|
||||
return -3; /* timeout or error */
|
||||
}
|
||||
|
||||
/* read results of transaction */
|
||||
byte = inb(smbus_io_base + SMBHSTCMD);
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - End.\n");
|
||||
return byte;
|
||||
}
|
||||
|
||||
int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0) {
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
|
||||
return -2; /* not ready */
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - Start.\n");
|
||||
/* set the command... */
|
||||
outb(val, smbus_io_base + SMBHSTCMD);
|
||||
|
||||
/* set the device I'm talking too */
|
||||
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
|
||||
|
||||
byte = inb(smbus_io_base + SMBHSTCTRL);
|
||||
byte &= 0xe3; /* Clear [4:2] */
|
||||
byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
|
||||
outb(byte, smbus_io_base + SMBHSTCTRL);
|
||||
|
||||
/* poll for transaction completion */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0) {
|
||||
return -3; /* timeout or error */
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - End.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0) {
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
|
||||
return -2; /* not ready */
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - Start.\n");
|
||||
/* set the command/address... */
|
||||
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
|
||||
|
||||
/* set the device I'm talking too */
|
||||
outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
|
||||
|
||||
byte = inb(smbus_io_base + SMBHSTCTRL);
|
||||
byte &= 0xe3; /* Clear [4:2] */
|
||||
byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
|
||||
outb(byte, smbus_io_base + SMBHSTCTRL);
|
||||
|
||||
/* poll for transaction completion */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0) {
|
||||
return -3; /* timeout or error */
|
||||
}
|
||||
|
||||
/* read results of transaction */
|
||||
byte = inb(smbus_io_base + SMBHSTDAT0);
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - End.\n");
|
||||
return byte;
|
||||
}
|
||||
|
||||
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
|
||||
{
|
||||
u8 byte;
|
||||
|
||||
if (smbus_wait_until_ready(smbus_io_base) < 0) {
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
|
||||
return -2; /* not ready */
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - Start.\n");
|
||||
/* set the command/address... */
|
||||
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
|
||||
|
||||
/* set the device I'm talking too */
|
||||
outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
|
||||
|
||||
/* output value */
|
||||
outb(val, smbus_io_base + SMBHSTDAT0);
|
||||
|
||||
byte = inb(smbus_io_base + SMBHSTCTRL);
|
||||
byte &= 0xe3; /* Clear [4:2] */
|
||||
byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
|
||||
outb(byte, smbus_io_base + SMBHSTCTRL);
|
||||
|
||||
/* poll for transaction completion */
|
||||
if (smbus_wait_until_done(smbus_io_base) < 0) {
|
||||
return -3; /* timeout or error */
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - End.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - Start.\n");
|
||||
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
|
||||
tmp = inl(AB_DATA);
|
||||
/* rpr 4.2
|
||||
* For certain revisions of the chip, the ABCFG registers,
|
||||
* with an address of 0x100NN (where 'N' is any hexadecimal
|
||||
* number), require an extra programming step.*/
|
||||
outl(0, AB_INDX);
|
||||
|
||||
tmp &= ~mask;
|
||||
tmp |= val;
|
||||
|
||||
/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
|
||||
outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
|
||||
outl(tmp, AB_DATA);
|
||||
outl(0, AB_INDX);
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n");
|
||||
}
|
||||
|
||||
void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - Start.\n");
|
||||
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
|
||||
tmp = inl(AB_DATA);
|
||||
/* rpr 4.2
|
||||
* For certain revisions of the chip, the ABCFG registers,
|
||||
* with an address of 0x100NN (where 'N' is any hexadecimal
|
||||
* number), require an extra programming step.*/
|
||||
outl(0, AB_INDX);
|
||||
|
||||
tmp &= ~mask;
|
||||
tmp |= val;
|
||||
|
||||
//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
|
||||
outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
|
||||
outl(tmp, AB_DATA);
|
||||
outl(0, AB_INDX);
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n");
|
||||
}
|
||||
|
||||
/* space = 0: AX_INDXC, AX_DATAC
|
||||
* space = 1: AX_INDXP, AX_DATAP
|
||||
*/
|
||||
void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - Start.\n");
|
||||
/* read axindc to tmp */
|
||||
outl(space << 29 | space << 3 | 0x30, AB_INDX);
|
||||
outl(axindc, AB_DATA);
|
||||
outl(0, AB_INDX);
|
||||
outl(space << 29 | space << 3 | 0x34, AB_INDX);
|
||||
tmp = inl(AB_DATA);
|
||||
outl(0, AB_INDX);
|
||||
|
||||
tmp &= ~mask;
|
||||
tmp |= val;
|
||||
|
||||
/* write tmp */
|
||||
outl(space << 29 | space << 3 | 0x30, AB_INDX);
|
||||
outl(axindc, AB_DATA);
|
||||
outl(0, AB_INDX);
|
||||
outl(space << 29 | space << 3 | 0x34, AB_INDX);
|
||||
outl(tmp, AB_DATA);
|
||||
outl(0, AB_INDX);
|
||||
printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - End.\n");
|
||||
}
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _SB900_SMBUS_H_
|
||||
#define _SB900_SMBUS_H_
|
||||
|
||||
//#include <stdint.h>
|
||||
|
||||
#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS
|
||||
|
||||
#define SMBHSTSTAT 0x0
|
||||
#define SMBSLVSTAT 0x1
|
||||
#define SMBHSTCTRL 0x2
|
||||
#define SMBHSTCMD 0x3
|
||||
#define SMBHSTADDR 0x4
|
||||
#define SMBHSTDAT0 0x5
|
||||
#define SMBHSTDAT1 0x6
|
||||
#define SMBHSTBLKDAT 0x7
|
||||
|
||||
#define SMBSLVCTRL 0x8
|
||||
#define SMBSLVCMD_SHADOW 0x9
|
||||
#define SMBSLVEVT 0xa
|
||||
#define SMBSLVDAT 0xc
|
||||
|
||||
#define AX_INDXC 0
|
||||
#define AX_INDXP 2
|
||||
#define AXCFG 4
|
||||
#define ABCFG 6
|
||||
#define RC_INDXC 1
|
||||
#define RC_INDXP 3
|
||||
|
||||
#define AB_INDX 0xCD8
|
||||
#define AB_DATA (AB_INDX+4)
|
||||
|
||||
/* Between 1-10 seconds, We should never timeout normally
|
||||
* Longer than this is just painful when a timeout condition occurs.
|
||||
*/
|
||||
#define SMBUS_TIMEOUT (100*1000*10)
|
||||
|
||||
#define abcfg_reg(reg, mask, val) \
|
||||
alink_ab_indx((ABCFG), (reg), (mask), (val))
|
||||
#define axcfg_reg(reg, mask, val) \
|
||||
alink_ab_indx((AXCFG), (reg), (mask), (val))
|
||||
#define axindxc_reg(reg, mask, val) \
|
||||
alink_ax_indx((AX_INDXC), (reg), (mask), (val))
|
||||
#define axindxp_reg(reg, mask, val) \
|
||||
alink_ax_indx((AX_INDXP), (reg), (mask), (val))
|
||||
#define rcindxc_reg(reg, port, mask, val) \
|
||||
alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
|
||||
#define rcindxp_reg(reg, port, mask, val) \
|
||||
alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
|
||||
|
||||
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
|
||||
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
|
||||
int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
|
||||
int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
|
||||
void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
|
||||
void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
|
||||
void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
|
||||
|
||||
#endif
|
|
@ -1 +1,5 @@
|
|||
subdirs-y += amd
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += $(src)/vendorcode/amd/agesa/f12
|
||||
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += $(src)/vendorcode/amd/agesa/f14
|
||||
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += $(src)/vendorcode/amd/cimx/sb800
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += $(src)/vendorcode/amd/cimx/sb900
|
||||
|
|
|
@ -1,21 +1,31 @@
|
|||
#*****************************************************************************
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
# Copyright (c) 2011, Advanced Micro Devices, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are met:
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# * Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
# its contributors may be used to endorse or promote products derived
|
||||
# from this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
#*****************************************************************************
|
||||
|
||||
# AGESA V5 Files
|
||||
AGESA_ROOT = src/vendorcode/amd/agesa/f14
|
||||
|
|
Loading…
Reference in New Issue