From 7c14ff0261951801bb7ff2aff8cfa25ca34b43ab Mon Sep 17 00:00:00 2001 From: Housong Zhang Date: Mon, 1 Nov 2021 11:00:09 +0800 Subject: [PATCH] soc/mediatek/mt8186: Add I2C driver support Add I2C controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Housong Zhang Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59296 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8186/Makefile.inc | 4 + src/soc/mediatek/mt8186/i2c.c | 143 ++++++++++++++++++++++ src/soc/mediatek/mt8186/include/soc/i2c.h | 70 +++++++++++ 3 files changed, 217 insertions(+) create mode 100644 src/soc/mediatek/mt8186/i2c.c create mode 100644 src/soc/mediatek/mt8186/include/soc/i2c.h diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index cb472cee2f..0646f6c97d 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += ../common/eint_event.c bootblock-y += ../common/flash_controller.c bootblock-y += gic.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -16,6 +17,7 @@ bootblock-y += ../common/wdt.c wdt.c verstage-y += ../common/auxadc.c verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c @@ -26,6 +28,7 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c @@ -37,6 +40,7 @@ ramstage-y += ../common/auxadc.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8186/i2c.c b/src/soc/mediatek/mt8186/i2c.c new file mode 100644 index 0000000000..a7f72acf2a --- /dev/null +++ b/src/soc/mediatek/mt8186/i2c.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#include +#include +#include +#include +#include +#include +#include + +struct mtk_i2c mtk_i2c_bus_controller[] = { + [0] = { + .i2c_regs = (void *)(I2C0_BASE), + .i2c_dma_regs = (void *)(I2C0_DMA_BASE), + }, + [1] = { + .i2c_regs = (void *)(I2C1_BASE), + .i2c_dma_regs = (void *)(I2C1_DMA_BASE), + }, + [2] = { + .i2c_regs = (void *)(I2C2_BASE), + .i2c_dma_regs = (void *)(I2C2_DMA_BASE), + }, + [3] = { + .i2c_regs = (void *)(I2C3_BASE), + .i2c_dma_regs = (void *)(I2C3_DMA_BASE), + }, + [4] = { + .i2c_regs = (void *)(I2C4_BASE), + .i2c_dma_regs = (void *)(I2C4_DMA_BASE), + }, + [5] = { + .i2c_regs = (void *)(I2C5_BASE), + .i2c_dma_regs = (void *)(I2C5_DMA_BASE), + }, + [6] = { + .i2c_regs = (void *)(I2C6_BASE), + .i2c_dma_regs = (void *)(I2C6_DMA_BASE), + }, + [7] = { + .i2c_regs = (void *)(I2C7_BASE), + .i2c_dma_regs = (void *)(I2C7_DMA_BASE), + }, + [8] = { + .i2c_regs = (void *)(I2C8_BASE), + .i2c_dma_regs = (void *)(I2C8_DMA_BASE), + }, + [9] = { + .i2c_regs = (void *)(I2C9_BASE), + .i2c_dma_regs = (void *)(I2C9_DMA_BASE), + }, +}; + +_Static_assert(ARRAY_SIZE(mtk_i2c_bus_controller) == I2C_BUS_NUMBER, + "Wrong size of mtk_i2c_bus_controller"); + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + [0] = { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + [1] = { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + [2] = { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + [3] = { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + [4] = { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + [5] = { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + [6] = { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, + [7] = { + PAD_FUNC(SDA7, SDA7), + PAD_FUNC(SCL7, SCL7), + }, + [8] = { + PAD_FUNC(SDA8, SDA8), + PAD_FUNC(SCL8, SCL8), + }, + [9] = { + PAD_FUNC(SDA9, SDA9), + PAD_FUNC(SCL9, SCL9), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed) +{ + mtk_i2c_speed_init(bus, speed); + mtk_i2c_set_gpio_pinmux(bus); +} + +void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) +{ + printk(BIOS_DEBUG, "LTIMING %x\nCLK_DIV %x\n", + read32(®s->ltiming), + read32(®s->clock_div)); +} + +void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl) +{ + write32(®s->clock_div, bus_ctrl->ac_timing.inter_clk_div); + write32(®s->timing, bus_ctrl->ac_timing.htiming); + write32(®s->ltiming, bus_ctrl->ac_timing.ltiming); + write32(®s->hs, bus_ctrl->ac_timing.hs); + write32(®s->ext_conf, bus_ctrl->ac_timing.ext); +} diff --git a/src/soc/mediatek/mt8186/include/soc/i2c.h b/src/soc/mediatek/mt8186/include/soc/i2c.h new file mode 100644 index 0000000000..4024e7de6b --- /dev/null +++ b/src/soc/mediatek/mt8186/include/soc/i2c.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8186 Functional Specification + * Chapter number: 5.10 + */ + +#ifndef SOC_MEDIATEK_MT8186_I2C_H +#define SOC_MEDIATEK_MT8186_I2C_H + +#include +#include + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, + I2C7, + I2C8, + I2C9, +}; + +#define I2C_BUS_NUMBER 10 +#define MAX_CLOCK_DIV 32 +#define I2C_CLK_HZ (UNIV2PLL_HZ / 20) + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus, uint32_t speed); + +#endif /* SOC_MEDIATEK_MT8186_I2C_H */