mb/google/rex/var/screebo: Update DTT settings for thermal control
update DTT settings for thermal control, as follows: 1.Cancel TCPU trip point and fine tune other protection temperature on the Critical policy table 2.Fine tune EC/Bios protection temperature BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1 changed files with 6 additions and 10 deletions
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@ -147,7 +147,6 @@ chip soc/intel/meteorlake
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TEMP_PCT(60, 60),
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TEMP_PCT(55, 50),
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TEMP_PCT(50, 40),
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TEMP_PCT(45, 30),
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}
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},
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[1] = {
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@ -159,7 +158,6 @@ chip soc/intel/meteorlake
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TEMP_PCT(60, 60),
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TEMP_PCT(55, 50),
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TEMP_PCT(50, 40),
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TEMP_PCT(45, 30),
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}
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},
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[2] = {
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@ -194,19 +192,17 @@ chip soc/intel/meteorlake
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## Passive Policy
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# TODO: below values are initial reference values only
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 85, 5000),
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[0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 5000),
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}"
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## Critical Policy
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# TODO: below values are initial reference values only
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN),
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[0] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
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}"
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## Power Limits Control
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