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mb/google/rex/var/screebo: Update DTT settings for thermal control

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update DTT settings for thermal control, as follows:

1.Cancel TCPU trip point and fine tune other protection temperature on the Critical policy table

2.Fine tune EC/Bios protection temperature

BUG=b:291217859
TEST=emerge-rex coreboot

Change-Id: I0e2ff6eea9fed71ad7680c1fac4921984b87aca5
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: zhongtian wu <wuzhongtian@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kun Liu 2023-10-08 15:29:30 +08:00 committed by Felix Held
parent 639d6c7c17
commit 7c193b9480
1 changed files with 6 additions and 10 deletions
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16
src/mainboard/google/rex/variants/screebo/overridetree.cb
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@ -147,7 +147,6 @@ chip soc/intel/meteorlake
TEMP_PCT(60, 60), TEMP_PCT(60, 60),
TEMP_PCT(55, 50), TEMP_PCT(55, 50),
TEMP_PCT(50, 40), TEMP_PCT(50, 40),
TEMP_PCT(45, 30),
} }
}, },
[1] = { [1] = {
@ -159,7 +158,6 @@ chip soc/intel/meteorlake
TEMP_PCT(60, 60), TEMP_PCT(60, 60),
TEMP_PCT(55, 50), TEMP_PCT(55, 50),
TEMP_PCT(50, 40), TEMP_PCT(50, 40),
TEMP_PCT(45, 30),
} }
}, },
[2] = { [2] = {
@ -194,19 +192,17 @@ chip soc/intel/meteorlake
## Passive Policy ## Passive Policy
# TODO: below values are initial reference values only # TODO: below values are initial reference values only
register "policies.passive" = "{ register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 85, 5000),
}" }"
## Critical Policy ## Critical Policy
# TODO: below values are initial reference values only # TODO: below values are initial reference values only
register "policies.critical" = "{ register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [0] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 105, SHUTDOWN),
}" }"
## Power Limits Control ## Power Limits Control