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exynos5420: Clock the mmc blocks off of the mpll. 

The exynos manual suggests hooking the mmc ip blocks to the mpll. They had
been set to use a different pll. This changes them over and modifies the
divider so that the frequency stays the same.

Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Gabe Black 2013-06-24 03:14:41 -07:00 committed by Stefan Reinauer
parent 04d6e01d43
commit 7c2ae7ae53
1 changed files with 2 additions and 2 deletions
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4
src/cpu/samsung/exynos5420/setup.h
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@ -222,7 +222,7 @@ struct exynos5_phy_control;
#define CLK_DIV_CPU0_VAL 0x01440020 #define CLK_DIV_CPU0_VAL 0x01440020
/* CLK_SRC_TOP */ /* CLK_SRC_TOP */
#define CLK_SRC_TOP0_VAL 0x12221222 #define CLK_SRC_TOP0_VAL 0x12222222
#define CLK_SRC_TOP1_VAL 0x00100200 #define CLK_SRC_TOP1_VAL 0x00100200
#define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x11111111 #define CLK_SRC_TOP3_VAL 0x11111111
@ -231,7 +231,7 @@ struct exynos5_phy_control;
#define CLK_SRC_TOP7_VAL 0x00022200 #define CLK_SRC_TOP7_VAL 0x00022200
/* CLK_DIV_TOP */ /* CLK_DIV_TOP */
#define CLK_DIV_TOP0_VAL 0x23712311 #define CLK_DIV_TOP0_VAL 0x23713311
#define CLK_DIV_TOP1_VAL 0x13100B00 #define CLK_DIV_TOP1_VAL 0x13100B00
#define CLK_DIV_TOP2_VAL 0x11101100 #define CLK_DIV_TOP2_VAL 0x11101100