nb/intel/x4x: Fix CAS latency detection and max memory detection
Now hardcode maximum memory frequency capability to 800MHz, as all chipsets in x4x family support PC2-6400 according to the datasheet. CAS latency detection also relies on this, and has been cleaned up. Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination, so disable this combination for now, and reduce to 667MHz instead. Still don't know why this is the case, but FSB1333/667 works. These changes should now allow existing configurations to continue working, while providing support for previously unworking configurations, due to previous buggy CAS latency detection code. TESTED: on GA-G41M-ES2L CPU: E5200 @ 2.50GHz (FSB 800MHz) 2x 1GB 667MHz hynix worked @ 667 1x 2GB 800Mhz ARAM worked @ 800 1x 1GB 667Mhz StarRam worked @ 667 2x 2GB 800Mhz (generic) worked @ 800 Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15818 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Damien Zammit
Kyösti Mälkki
parent
40d93494c3
commit
7c2e5396a3
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@ -111,10 +111,9 @@ static void sdram_read_spds(struct sysinfo *s)
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s->dimms[i].chip_capacity = s->dimms[i].banks;
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s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12;
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s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9;
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s->dimms[i].cas_latencies = 0x70; // 6,5,4 CL
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s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18];
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s->dimms[i].cas_latencies = s->dimms[i].spd_data[18];
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if (s->dimms[i].cas_latencies == 0)
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s->dimms[i].cas_latencies = 0x70;
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s->dimms[i].cas_latencies = 0x60; // 6,5 CL
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s->dimms[i].tAAmin = s->dimms[i].spd_data[26];
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s->dimms[i].tCKmin = s->dimms[i].spd_data[25];
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s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1;
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@ -248,13 +247,6 @@ static void sdram_read_spds(struct sysinfo *s)
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}
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}
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static u8 lsbpos(u8 val) //Forward
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{
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u8 i;
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for (i = 0; (i < 8) && ((val & (1 << i)) == 0); i++);
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return i;
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}
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static u8 msbpos(u8 val) //Reverse
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{
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u8 i;
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@ -264,8 +256,6 @@ static u8 msbpos(u8 val) //Reverse
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static void mchinfo_ddr2(struct sysinfo *s)
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{
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u8 capablefreq, maxfreq;
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const u32 eax = cpuid_ext(0x04, 0).eax;
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s->cores = ((eax >> 26) & 0x3f) + 1;
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printk(BIOS_WARNING, "%d CPU cores\n", s->cores);
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@ -284,19 +274,7 @@ static void mchinfo_ddr2(struct sysinfo *s)
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printk(BIOS_WARNING, "AMT enabled\n");
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}
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maxfreq = MEM_CLOCK_800MHz;
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capablefreq = (u8)((pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f);
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capablefreq &= 0x7;
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if (capablefreq)
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maxfreq = capablefreq + 1;
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if (maxfreq > MEM_CLOCK_800MHz)
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maxfreq = MEM_CLOCK_800MHz;
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if (maxfreq < MEM_CLOCK_667MHz)
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maxfreq = MEM_CLOCK_667MHz;
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s->max_ddr2_mhz = (maxfreq == MEM_CLOCK_800MHz) ? 800 : 667;
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s->max_ddr2_mhz = 800; // All chipsets in x4x support up to 800MHz DDR2
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printk(BIOS_WARNING, "Capable of DDR2 of %d MHz or lower\n", s->max_ddr2_mhz);
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if (!(capid & (1<<(48-32)))) {
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@ -308,12 +286,15 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
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{
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u8 i;
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u8 commoncas = 0;
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u8 cas;
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u8 lowcas;
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u8 highcas;
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u8 currcas;
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u8 currfreq;
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u8 maxfreq;
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u8 freq = 0;
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// spdidx,cycletime @CAS 5 6
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u8 idx800[7][2] = {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {23,0x30}, {9,0x25}};
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int found = 0;
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// Find max FSB speed
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switch (MCHBAR32(0xc00) & 0x7) {
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case 0x0:
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@ -334,11 +315,13 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
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// Max RAM speed
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if (s->spd_type == DDR2) {
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// Choose max memory frequency for MCH as previously detected
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freq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;
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// FIXME: Limit memory speed to 667MHz if FSB is 1333MHz
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maxfreq = (s->max_fsb == FSB_CLOCK_1333MHz)
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? MEM_CLOCK_667MHz : MEM_CLOCK_800MHz;
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// Choose common CAS latency from {6,5}, 4 does not work
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commoncas = 0x60;
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// Detect a common CAS latency (Choose from 6,5,4 CL)
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commoncas = 0x70;
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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commoncas &= s->dimms[i].cas_latencies;
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}
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@ -346,74 +329,41 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
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die("No common CAS among dimms\n");
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}
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// Start with fastest common CAS
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cas = 0;
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highcas = msbpos(commoncas);
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lowcas = lsbpos(commoncas);
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while (cas == 0 && highcas >= lowcas) {
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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switch (freq) {
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case MEM_CLOCK_800MHz:
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if ((s->dimms[i].spd_data[9] > 0x25) ||
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(s->dimms[i].spd_data[10] > 0x40)) {
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// CAS too fast, lower it
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highcas--;
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break;
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} else {
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cas = highcas;
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}
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break;
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case MEM_CLOCK_667MHz:
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default:
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if ((s->dimms[i].spd_data[9] > 0x30) ||
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(s->dimms[i].spd_data[10] > 0x45)) {
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// CAS too fast, lower it
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highcas--;
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break;
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} else {
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cas = highcas;
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}
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break;
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}
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}
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}
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if (highcas < lowcas) {
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// Timings not supported by MCH, lower the frequency
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freq--;
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cas = 0;
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highcas = msbpos(commoncas);
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lowcas = lsbpos(commoncas);
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while (cas == 0 && highcas >= lowcas) {
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// Working from fastest to slowest,
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// fast->slow 5@800 6@800 5@667
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found = 0;
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for (currcas = 5; currcas <= msbpos(commoncas); currcas++) {
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currfreq = maxfreq;
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if (currfreq == MEM_CLOCK_800MHz) {
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found = 1;
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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switch (freq) {
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case MEM_CLOCK_800MHz:
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if ((s->dimms[i].spd_data[23] > 0x25) ||
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(s->dimms[i].spd_data[24] > 0x40)) {
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// CAS too fast, lower it
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highcas--;
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break;
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} else {
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cas = highcas;
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}
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break;
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case MEM_CLOCK_667MHz:
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default:
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if ((s->dimms[i].spd_data[23] > 0x30) ||
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(s->dimms[i].spd_data[24] > 0x45)) {
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// CAS too fast, lower it
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highcas--;
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break;
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} else {
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cas = highcas;
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}
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break;
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if (s->dimms[i].spd_data[idx800[currcas][0]] > idx800[currcas][1]) {
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// this is too fast
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found = 0;
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}
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}
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if (found)
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break;
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}
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}
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if (!found) {
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currcas = 5;
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currfreq = MEM_CLOCK_667MHz;
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found = 1;
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FOR_EACH_POPULATED_DIMM(s->dimms, i) {
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if (s->dimms[i].spd_data[9] > 0x30) {
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// this is too fast
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found = 0;
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}
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}
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}
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s->selected_timings.mem_clk = freq;
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s->selected_timings.CAS = cas;
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if (!found)
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die("No valid CAS/frequencies detected\n");
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s->selected_timings.mem_clk = currfreq;
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s->selected_timings.CAS = currcas;
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} else { // DDR3
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// Limit frequency for MCH
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@ -293,11 +293,10 @@ static void launch_ddr2(struct sysinfo *s)
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if (s->selected_timings.CAS == 5) {
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launch2 = 0x00220201;
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} else if ((s->selected_timings.mem_clk == MEM_CLOCK_800MHz) &&
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(s->selected_timings.CAS == 6)) {
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} else if (s->selected_timings.CAS == 6) {
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launch2 = 0x00230302;
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} else {
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die("Unsupported CAS & Frequency combination detected\n");
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die("Unsupported CAS\n");
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}
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FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
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