From 7c2f57a4c7aee8ed63001d5db686917d17cf82f6 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 13 Feb 2022 18:23:37 -0600 Subject: [PATCH] soc/intel/cnl: Enable CSE FW sync for CSE LITE SKU Boards based on google/puff baseboard (hatch variant) use CSE LITE, which utilizes RO and RW firmware. If the CSE does not switch to the RW firmware, the HECI1 interface is disabled, and dependent drivers (like SOF audio firmware) fail to load. Use the same logic as other platforms utilizing CSE LITE (eg, TGL/JSL) to check if an ME RW firmware update is available, and if not jump to the onboard RW firmware. Test: built/boot Manjaro 21.x on google/wyvern, verify CSE RW firmware loaded via cbmem console, HECI1 interface is present vis lspci, and the SOF DSP firmware is correctly loaded via dmesg. Change-Id: I0ae21adde4a64bbcc5fa4fb144436a0430e92280 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/61909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak --- src/soc/intel/cannonlake/romstage/romstage.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index a83cf616e8..236a122cb4 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -130,6 +130,16 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!s3wake) { + /* + * cse_fw_sync() must be called after DRAM initialization as + * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) + * is expected to be executed after DRAM initialization. + */ + + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_fw_sync(); + save_dimm_info(); + } }