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soc/intel/apollolake: Reinstate APL_SKIP_SET_POWER_LIMITS 

The config option APL_SKIP_SET_POWER_LIMITS was accidentally left out
during the set_power_limits refactor (SHA 2adb50d32e). This patch
reinstates the config option which will cause APL boards to not set any
power limits.

TEST=util/abuild/abuild -p none -t siemens/mc_apl1 -a

Change-Id: Iec9f9f340d50a1212b6ef20c2c0e1b66385ae1b2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Tim Wawrzynczak 2020-05-27 10:22:45 -06:00
parent bebb2a1705
commit 7c34865c92
1 changed files with 8 additions and 4 deletions
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12
src/soc/intel/apollolake/chip.c
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@ -322,10 +322,14 @@ static void soc_init(void *data)
/* Allocate ACPI NVS in CBMEM */ /* Allocate ACPI NVS in CBMEM */
cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t)); cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t));
config = config_of_soc(); if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
/* Set RAPL MSR for Package power limits */ printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
soc_config = &config->power_limits_config; } else {
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); config = config_of_soc();
/* Set RAPL MSR for Package power limits */
soc_config = &config->power_limits_config;
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
}
/* /*
* FSP-S routes SCI to IRQ 9. With the help of this function you can * FSP-S routes SCI to IRQ 9. With the help of this function you can