northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12027 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson
Martin Roth
parent
5173bb7d9d
commit
7c55f374d1
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@ -273,7 +273,13 @@ static const struct {
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/* Link Global Retry Control Register */
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{ 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
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0x00073900, 0x00073F00 },
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0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7,
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HtRetryCrcDatInsDynEn = 0x1,
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HtRetryCrcCmdPackDynEn = 0x1,
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HtRetryCrcDatIns = 0x4,
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HtRetryCrcCmdPack = 0x1,
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ForceErrType = 0x0,
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MultRetryErr = 0x0 */
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/* Errata 351
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* System software should program the Link Extended Control Registers[LS2En]
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@ -120,21 +120,21 @@ enumerations
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10 21 42ms
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10 22 84ms
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11 0 Auto
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11 1 2.6GHz
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11 2 2.4GHz
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11 3 2.2GHz
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11 4 2.0GHz
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11 5 1.8GHz
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11 6 1.6GHz
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11 7 1.4GHz
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11 8 1.2GHz
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11 9 1.0GHz
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11 10 800MHz
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11 11 600MHz
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11 12 500MHz
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11 13 400MHz
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11 14 300MHz
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11 15 200MHz
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11 1 3.2GHz
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11 2 3.0GHz
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11 3 2.8GHz
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11 4 2.6GHz
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11 5 2.4GHz
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11 6 2.2GHz
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11 7 2.0GHz
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11 8 1.8GHz
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11 9 1.6GHz
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11 10 1.4GHz
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11 11 1.2GHz
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11 12 1.0GHz
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11 13 800MHz
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11 14 600MHz
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11 15 500MHz
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12 0 1.5V
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12 1 1.35V
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12 2 1.25V
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -58,6 +59,7 @@
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#define HTHOST_LINK_CAPABILITY_REG 0x00
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#define HTHOST_LINK_CONTROL_REG 0x04
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#define HTHOST_FREQ_REV_REG 0x08
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#define HTHOST_FREQ_REV_REG_2 0x1c
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#define HT_HOST_REV_REV3 0x60
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#define HTHOST_FEATURE_CAP_REG 0x0C
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#define HTHOST_BUFFER_COUNT_REG 0x10
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@ -123,10 +125,10 @@ typedef struct
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/* This section is for keeping track of capabilities and possible configurations */
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BOOL RegangCap;
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u16 PrvFrequencyCap;
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uint32_t PrvFrequencyCap;
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u8 PrvWidthInCap;
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u8 PrvWidthOutCap;
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u16 CompositeFrequencyCap;
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uint32_t CompositeFrequencyCap;
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} sPortDescriptor;
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@ -48,28 +48,32 @@
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#define APIC_Base_BSP 8
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#define APIC_Base 0x1b
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#define NVRAM_LIMIT_HT_SPEED_200 0xf
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#define NVRAM_LIMIT_HT_SPEED_300 0xe
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#define NVRAM_LIMIT_HT_SPEED_400 0xd
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#define NVRAM_LIMIT_HT_SPEED_500 0xc
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#define NVRAM_LIMIT_HT_SPEED_600 0xb
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#define NVRAM_LIMIT_HT_SPEED_800 0xa
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#define NVRAM_LIMIT_HT_SPEED_1000 0x9
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#define NVRAM_LIMIT_HT_SPEED_1200 0x8
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#define NVRAM_LIMIT_HT_SPEED_1400 0x7
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#define NVRAM_LIMIT_HT_SPEED_1600 0x6
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#define NVRAM_LIMIT_HT_SPEED_1800 0x5
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#define NVRAM_LIMIT_HT_SPEED_2000 0x4
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#define NVRAM_LIMIT_HT_SPEED_2200 0x3
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#define NVRAM_LIMIT_HT_SPEED_2400 0x2
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#define NVRAM_LIMIT_HT_SPEED_2600 0x1
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#define NVRAM_LIMIT_HT_SPEED_200 0x12
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#define NVRAM_LIMIT_HT_SPEED_300 0x11
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#define NVRAM_LIMIT_HT_SPEED_400 0x10
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#define NVRAM_LIMIT_HT_SPEED_500 0xf
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#define NVRAM_LIMIT_HT_SPEED_600 0xe
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#define NVRAM_LIMIT_HT_SPEED_800 0xd
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#define NVRAM_LIMIT_HT_SPEED_1000 0xc
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#define NVRAM_LIMIT_HT_SPEED_1200 0xb
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#define NVRAM_LIMIT_HT_SPEED_1400 0xa
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#define NVRAM_LIMIT_HT_SPEED_1600 0x9
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#define NVRAM_LIMIT_HT_SPEED_1800 0x8
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#define NVRAM_LIMIT_HT_SPEED_2000 0x7
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#define NVRAM_LIMIT_HT_SPEED_2200 0x6
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#define NVRAM_LIMIT_HT_SPEED_2400 0x5
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#define NVRAM_LIMIT_HT_SPEED_2600 0x4
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#define NVRAM_LIMIT_HT_SPEED_2800 0x3
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#define NVRAM_LIMIT_HT_SPEED_3000 0x2
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#define NVRAM_LIMIT_HT_SPEED_3200 0x1
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#define NVRAM_LIMIT_HT_SPEED_AUTO 0x0
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static const uint16_t ht_speed_limit[16] =
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{0xFFFF, 0x7FFF, 0x3FFF, 0x1FFF,
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0x0FFF, 0x07FF, 0x03FF, 0x01FF,
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0x00FF, 0x007F, 0x003F, 0x001F,
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0x000F, 0x0007, 0x0003, 0x0001};
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static const uint32_t ht_speed_limit[20] =
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{0xFFFFF, 0xFFFFF, 0x7FFFF, 0x3FFFF,
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0x0FFFF, 0x07FFF, 0x03FFF, 0x01FFF,
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0x00FFF, 0x007FF, 0x003FF, 0x001FF,
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0x000FF, 0x0007F, 0x0003F, 0x0001F,
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0x0000F, 0x00007, 0x00003, 0x00001};
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static const struct ht_speed_limit_map_t {
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uint16_t mhz;
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@ -91,9 +95,12 @@ static const struct ht_speed_limit_map_t {
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{2200, NVRAM_LIMIT_HT_SPEED_2200},
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{2400, NVRAM_LIMIT_HT_SPEED_2400},
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{2600, NVRAM_LIMIT_HT_SPEED_2600},
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{2800, NVRAM_LIMIT_HT_SPEED_2800},
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{3000, NVRAM_LIMIT_HT_SPEED_3000},
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{3200, NVRAM_LIMIT_HT_SPEED_3200},
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};
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static const uint16_t ht_speed_mhz_to_hw(uint16_t mhz)
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static const uint32_t ht_speed_mhz_to_hw(uint16_t mhz)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(ht_speed_limit_map); i++)
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@ -452,7 +459,7 @@ static void htDiscoveryFloodFill(sMainData *pDat)
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/* Set currentNode's NodeID field to currentNode */
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pDat->nb->writeNodeID(currentNode, currentNode, pDat->nb);
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/* Enable routing tables on currentNode*/
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/* Enable routing tables on currentNode */
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pDat->nb->enableRoutingTables(currentNode, pDat->nb);
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for (currentLinkID = 0; currentLinkID < pDat->nb->maxLinks; currentLinkID++)
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@ -1427,19 +1434,30 @@ static void regangLinks(sMainData *pDat)
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static void selectOptimalWidthAndFrequency(sMainData *pDat)
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{
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u8 i, j;
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u32 temp;
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u16 cbPCBFreqLimit;
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u16 cbPCBFreqLimit_NVRAM;
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uint32_t temp;
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uint32_t cbPCBFreqLimit;
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uint32_t cbPCBFreqLimit_NVRAM;
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u8 cbPCBABDownstreamWidth;
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u8 cbPCBBAUpstreamWidth;
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cbPCBFreqLimit_NVRAM = 0xFFFF;
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cbPCBFreqLimit_NVRAM = 0xfffff;
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if (get_option(&temp, "hypertransport_speed_limit") == CB_SUCCESS)
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cbPCBFreqLimit_NVRAM = ht_speed_limit[temp & 0xf];
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if (!is_fam15h()) {
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/* FIXME
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* By default limit frequency to 2.6 GHz as there are residual
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* problems with HT v3.1 implementation on at least some Socket G34
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* mainboards / Fam10h CPUs.
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* Debug the issues and reenable this...
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*/
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if (cbPCBFreqLimit_NVRAM > 0xffff)
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cbPCBFreqLimit_NVRAM = 0xffff;
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}
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for (i = 0; i < pDat->TotalLinks*2; i += 2)
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{
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cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration
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cbPCBFreqLimit = 0xfffff; // Maximum allowed by autoconfiguration
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if (pDat->HtBlock->ht_link_configuration)
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cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit);
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cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM);
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@ -1484,17 +1502,18 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat)
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}
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}
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temp = pDat->PortList[i].PrvFrequencyCap;
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temp &= pDat->PortList[i+1].PrvFrequencyCap;
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temp &= cbPCBFreqLimit;
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pDat->PortList[i].CompositeFrequencyCap = (u16)temp;
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pDat->PortList[i+1].CompositeFrequencyCap = (u16)temp;
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pDat->PortList[i].CompositeFrequencyCap = temp;
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pDat->PortList[i+1].CompositeFrequencyCap = temp;
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ASSERT (temp != 0);
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for (j = 15; ; j--)
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for (j = 19; ; j--)
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{
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if (temp & ((u32)1 << j))
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if ((j == 16) || (j == 15))
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continue;
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if (temp & ((uint32_t)1 << j))
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break;
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}
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@ -1638,12 +1657,14 @@ static void hammerSublinkFixup(sMainData *pDat)
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/* Remove hiFreq from the list of valid frequencies */
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temp = temp & ~((uint32)1 << hiFreq);
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ASSERT (temp != 0);
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pDat->PortList[hiIndex].CompositeFrequencyCap = (uint16)temp;
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pDat->PortList[hiIndex+1].CompositeFrequencyCap = (uint16)temp;
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pDat->PortList[hiIndex].CompositeFrequencyCap = temp;
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pDat->PortList[hiIndex+1].CompositeFrequencyCap = temp;
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for (k = 15; ; k--)
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for (k = 19; ; k--)
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{
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if (temp & ((u32)1 << k))
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if ((j == 16) || (j == 15))
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continue;
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if (temp & ((uint32_t)1 << k))
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break;
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}
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@ -49,6 +49,9 @@
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#define HT_FREQUENCY_2200M 12
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#define HT_FREQUENCY_2400M 13
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#define HT_FREQUENCY_2600M 14
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#define HT_FREQUENCY_2800M 17
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#define HT_FREQUENCY_3000M 18
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#define HT_FREQUENCY_3200M 19
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/* Frequency Limit equates for call backs which take a frequency supported mask. */
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#define HT_FREQUENCY_LIMIT_200M 1
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@ -65,6 +68,9 @@
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#define HT_FREQUENCY_LIMIT_2200M 0x1FFF
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#define HT_FREQUENCY_LIMIT_2400M 0x3FFF
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#define HT_FREQUENCY_LIMIT_2600M 0x7FFF
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#define HT_FREQUENCY_LIMIT_2800M 0x3FFFF
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#define HT_FREQUENCY_LIMIT_3000M 0x7FFFF
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#define HT_FREQUENCY_LIMIT_3200M 0xFFFFF
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/*
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* Event Notify definitions
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@ -220,7 +226,7 @@ typedef struct {
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* @param[in] u8 Link = The Device's link number (0 or 1)
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* @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In
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* @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out
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* @param[in,out] u16* FreqCap = modify to change the link's frequency capability
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* @param[in,out] u32* FreqCap = modify to change the link's frequency capability
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*
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* ---------------------------------------------------------------------------------------
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*/
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@ -235,7 +241,7 @@ typedef struct {
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u8 Link,
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u8 *LinkWidthIn,
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u8 *LinkWidthOut,
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u16 *FreqCap
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u32 *FreqCap
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);
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/**----------------------------------------------------------------------------------------
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@ -258,7 +264,7 @@ typedef struct {
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* @param[in] u8 linkB = The link on that node
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* @param[in,out] u8* ABLinkWidthLimit = modify to change the Link Witdh In
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* @param[in,out] u8* BALinkWidthLimit = modify to change the Link Witdh Out
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* @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability
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* @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability
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*
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* ---------------------------------------------------------------------------------------
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*/
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@ -269,7 +275,7 @@ typedef struct {
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u8 LinkB,
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u8 *ABLinkWidthLimit,
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u8 *BALinkWidthLimit,
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u16 *PCBFreqCap
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u32 *PCBFreqCap
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);
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/**----------------------------------------------------------------------------------------
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@ -291,7 +297,7 @@ typedef struct {
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* @param[in] u8 Depth = The depth in the I/O chain from the Host
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* @param[in,out] u8* DownstreamLinkWidthLimit = modify to change the Link Witdh In
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* @param[in,out] u8* UpstreamLinkWidthLimit = modify to change the Link Witdh Out
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* @param[in,out] u16* PCBFreqCap = modify to change the link's frequency capability
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* @param[in,out] u32* PCBFreqCap = modify to change the link's frequency capability
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*
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* ---------------------------------------------------------------------------------------
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*/
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@ -301,7 +307,7 @@ typedef struct {
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u8 Depth,
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u8 *DownstreamLinkWidthLimit,
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u8 *UpstreamLinkWidthLimit,
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u16 *PCBFreqCap
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u32 *PCBFreqCap
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);
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/**----------------------------------------------------------------------------------------
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@ -1310,7 +1310,7 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb)
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* @return Frequency mask
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*
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******************************************************************************/
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static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb)
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static uint32_t ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb)
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{
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/* only up to HT1 speeds */
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return (HT_FREQUENCY_LIMIT_HT1_ONLY);
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@ -1331,26 +1331,43 @@ static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb)
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* @return = Frequency mask
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*
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******************************************************************************/
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static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb)
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static uint32_t fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb)
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{
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u8 nbCOF;
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u16 supported;
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uint32_t supported;
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nbCOF = getMinNbCOF();
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/*
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* nbCOF is minimum northbridge speed in hundreds of MHz.
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* HT can not go faster than the minimum speed of the northbridge.
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*/
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if ((nbCOF >= 6) && (nbCOF <= 26))
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if ((nbCOF >= 6) && (nbCOF < 10))
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{
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/* Generation 1 HT link frequency */
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/* Convert frequency to bit and all less significant bits,
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* by setting next power of 2 and subtracting 1.
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*/
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supported = ((u16)1 << ((nbCOF >> 1) + 2)) - 1;
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supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1;
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}
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else if (nbCOF > 26)
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else if ((nbCOF >= 10) && (nbCOF <= 32))
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{
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supported = HT_FREQUENCY_LIMIT_2600M;
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/* Generation 3 HT link frequency
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* Assume error retry is enabled on all Gen 3 links
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*/
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if (is_gt_rev_d()) {
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nbCOF *= 2;
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if (nbCOF > 32)
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nbCOF = 32;
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}
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/* Convert frequency to bit and all less significant bits,
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* by setting next power of 2 and subtracting 1.
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*/
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supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1;
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}
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else if (nbCOF > 32)
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{
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supported = HT_FREQUENCY_LIMIT_3200M;
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}
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/* unlikely cases, but include as a defensive measure, also avoid trick above */
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else if (nbCOF == 4)
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@ -1405,8 +1422,13 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb)
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pDat->PortList[i].PrvWidthInCap = convertBitsToWidth((u8)temp, pDat->nb);
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AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG, 31, 16, &temp);
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pDat->PortList[i].PrvFrequencyCap = (u16)temp & 0x7FFF
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& nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); /* Mask off bit 15, reserved value */
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pDat->PortList[i].PrvFrequencyCap = temp & 0x7FFF /* Mask off bit 15, reserved value */
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& nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb);
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if (is_gt_rev_d()) {
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AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG_2, 15, 1, &temp);
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temp &= 0x7; /* Mask off reserved values */
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pDat->PortList[i].PrvFrequencyCap |= (temp << 17);
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}
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}
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else
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{
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@ -1463,7 +1485,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb)
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{
|
||||
u8 i;
|
||||
SBDFO linkBase;
|
||||
u32 temp, widthin, widthout, bits;
|
||||
u32 temp, temp2, frequency_index, widthin, widthout, bits;
|
||||
|
||||
for (i = 0; i < pDat->TotalLinks*2; i++)
|
||||
{
|
||||
|
|
@ -1524,10 +1546,19 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb)
|
|||
temp = pDat->PortList[i].SelFrequency;
|
||||
if (pDat->PortList[i].Type == PORTLIST_TYPE_CPU)
|
||||
{
|
||||
ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_2600M)
|
||||
ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_3200M)
|
||||
|| (temp == HT_FREQUENCY_200M) || (temp == HT_FREQUENCY_400M));
|
||||
frequency_index = temp;
|
||||
if (temp > 0xf) {
|
||||
temp2 = (temp >> 4) & 0x1;
|
||||
temp &= 0xf;
|
||||
} else {
|
||||
temp2 = 0x0;
|
||||
}
|
||||
if (is_gt_rev_d())
|
||||
AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2);
|
||||
AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp);
|
||||
if (temp > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz */
|
||||
if (frequency_index > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 3200MHz */
|
||||
{
|
||||
/* Enable for Gen3 frequencies */
|
||||
temp = 1;
|
||||
|
|
@ -1557,7 +1588,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb)
|
|||
SBDFO currentPtr;
|
||||
BOOL isFound;
|
||||
|
||||
ASSERT(temp <= HT_FREQUENCY_2600M);
|
||||
ASSERT(temp <= HT_FREQUENCY_3200M);
|
||||
/* Write the frequency setting */
|
||||
AmdPCIWriteBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 11, 8, &temp);
|
||||
|
||||
|
|
@ -1718,6 +1749,9 @@ static void fam0fWriteHTLinkCmdBufferAlloc(u8 node, u8 link, u8 req, u8 preq, u8
|
|||
/* Probe Command Buffers */
|
||||
temp = prb;
|
||||
AmdPCIWriteBits(currentPtr, 15, 12, &temp);
|
||||
/* LockBc */
|
||||
temp = 1;
|
||||
AmdPCIWriteBits(currentPtr, 31, 31, &temp);
|
||||
}
|
||||
#endif /* HT_BUILD_NC_ONLY */
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -103,7 +104,7 @@ struct cNorthBridge
|
|||
/* Public Interfaces for northbridge clients, Optimization */
|
||||
u8 (*convertBitsToWidth)(u8 value, cNorthBridge *nb);
|
||||
u8 (*convertWidthToBits)(u8 value, cNorthBridge *nb);
|
||||
u16 (*northBridgeFreqMask)(u8 node, cNorthBridge *nb);
|
||||
uint32_t (*northBridgeFreqMask)(u8 node, cNorthBridge *nb);
|
||||
void (*gatherLinkData)(sMainData *pDat, cNorthBridge *nb);
|
||||
void (*setLinkData)(sMainData *pDat, cNorthBridge *nb);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue