mb/qemu-i440fx,soc/nvidia: Fix coverity reported defects

In reality the expression should not overflow as the value
fits in 32 bits.

Change-Id: I50d83dce25a4d464e1c979502c290d8ecd733018
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Kyösti Mälkki 2022-07-01 18:50:26 +03:00 committed by Felix Held
parent cb08c7937d
commit 7c60068b23
2 changed files with 5 additions and 5 deletions

View File

@ -47,7 +47,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
int i440fx = (nbid == 0x1237); int i440fx = (nbid == 0x1237);
int q35 = (nbid == 0x29c0); int q35 = (nbid == 0x29c0);
struct resource *res; struct resource *res;
unsigned long tomk = 0; uint64_t tomk = 0;
int idx = 10; int idx = 10;
FWCfgFile f; FWCfgFile f;
@ -93,7 +93,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
/* qemu older than 1.7, or reading etc/e820 failed. Fallback to cmos. */ /* qemu older than 1.7, or reading etc/e820 failed. Fallback to cmos. */
tomk = qemu_get_memory_size(); tomk = qemu_get_memory_size();
uint64_t high = qemu_get_high_memory_size(); uint64_t high = qemu_get_high_memory_size();
printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM below 4G.\n", tomk / 1024); printk(BIOS_DEBUG, "QEMU: cmos: %llu MiB RAM below 4G.\n", tomk / 1024);
printk(BIOS_DEBUG, "QEMU: cmos: %llu MiB RAM above 4G.\n", high / 1024); printk(BIOS_DEBUG, "QEMU: cmos: %llu MiB RAM above 4G.\n", high / 1024);
/* Report the memory regions. */ /* Report the memory regions. */

View File

@ -16,13 +16,13 @@
*/ */
static void soc_read_resources(struct device *dev) static void soc_read_resources(struct device *dev)
{ {
u32 lcdbase = fb_base_mb(); uint64_t lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB; uint64_t fb_size = FB_SIZE_MB;
ram_from_to(dev, 0, (uintptr_t)_dram, (sdram_max_addressable_mb() - fb_size) * MiB); ram_from_to(dev, 0, (uintptr_t)_dram, (sdram_max_addressable_mb() - fb_size) * MiB);
mmio_range(dev, 1, lcdbase * MiB, fb_size * MiB); mmio_range(dev, 1, lcdbase * MiB, fb_size * MiB);
ram_from_to(dev, 2, sdram_max_addressable_mb() * MiB, ram_from_to(dev, 2, sdram_max_addressable_mb() * (uint64_t)MiB,
(uintptr_t)_dram + sdram_size_mb() * (uint64_t)MiB); (uintptr_t)_dram + sdram_size_mb() * (uint64_t)MiB);
} }