Fix code that would trip -Wtype-limits

This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.

Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/console/vtxprintf.c

@@ -56,8 +56,10 @@ static int number(void (*tx_byte)(unsigned char byte, void *data),
 	int count = 0;
 #ifdef SUPPORT_64BIT_INTS
 	unsigned long long num = inum;
+	long long snum = num;
 #else
-	unsigned long num = (long)inum;
+	unsigned long num = (unsigned long)inum;
+	long snum = (long)num;
 
 	if (num != inum) {
 		/* Alert user to an incorrect result by printing #^!. */
@@ -76,9 +78,9 @@ static int number(void (*tx_byte)(unsigned char byte, void *data),
 	c = (type & ZEROPAD) ? '0' : ' ';
 	sign = 0;
 	if (type & SIGN) {
-		if ((signed long long)num < 0) {
+		if (snum < 0) {
 			sign = '-';
-			num = -num;
+			num = -snum;
 			size--;
 		} else if (type & PLUS) {
 			sign = '+';

src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c

@@ -45,9 +45,6 @@ static efi_return_status_t mp_get_processor_info(const
 	efi_uintn_t processor_number,
 	efi_processor_information *processor_info_buffer)
 {
-	if (cpu_index() < 0)
-		return FSP_DEVICE_ERROR;
-
 	if (processor_info_buffer == NULL)
 		return FSP_INVALID_PARAMETER;
 
@@ -71,9 +68,6 @@ static efi_return_status_t mp_startup_all_aps(const
 	efi_ap_procedure procedure, efi_boolean_t ignored3,
 	efi_uintn_t timeout_usec, void *argument)
 {
-	if (cpu_index() < 0)
-		return FSP_DEVICE_ERROR;
-
 	if (procedure == NULL)
 		return FSP_INVALID_PARAMETER;
 
@@ -91,9 +85,6 @@ static efi_return_status_t mp_startup_this_ap(const
 	efi_ap_procedure procedure, efi_uintn_t processor_number,
 	efi_uintn_t timeout_usec, void *argument)
 {
-	if (cpu_index() < 0)
-		return FSP_DEVICE_ERROR;
-
 	if (processor_number > get_cpu_count())
 		return FSP_NOT_FOUND;
 

src/drivers/pc80/rtc/mc146818rtc.c

@@ -39,6 +39,9 @@
 #define LB_CKS_LOC		0
 #endif
 
+/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */
+#pragma GCC diagnostic ignored "-Wtype-limits"
+
 #include <smp/spinlock.h>
 
 #if (defined(__PRE_RAM__) &&	\

src/drivers/spi/spi_flash.c

@@ -339,7 +339,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi,
 	printk(BIOS_INFO, "Manufacturer: %02x\n", *idp);
 
 	/* search the table for matches in shift and id */
-	for (i = 0; i < ARRAY_SIZE(flashes); ++i)
+	for (i = 0; i < (int)ARRAY_SIZE(flashes); ++i)
 		if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
 			/* we have a match, call probe */
 			if (flashes[i].probe(spi, idp, flash) == 0) {

src/mainboard/google/foster/pmic.c

@@ -34,10 +34,6 @@ struct max77620_init_reg {
 	u8 delay;
 };
 
-static struct max77620_init_reg init_list[] = {
-	/* TODO */
-};
-
 static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
 {
 	if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) {
@@ -51,20 +47,8 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
 	}
 }
 
-static void pmic_slam_defaults(unsigned bus)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(init_list); i++) {
-		struct max77620_init_reg *reg = &init_list[i];
-		pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
-	}
-}
-
 void pmic_init(unsigned bus)
 {
-	/* Restore PMIC POR defaults, in case kernel changed 'em */
-	pmic_slam_defaults(bus);
-
 	/* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
 	pmic_write_reg(bus, MAX77620_GPIO5_REG, 0x09, 1);
 

src/mainboard/google/octopus/romstage.c

@@ -44,7 +44,7 @@ void mainboard_save_dimm_info(void)
 
 	if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
 		/* Fall back on part numbers encoded in lp4cfg array. */
-		if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) {
+		if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) {
 			save_dimm_info_by_sku_config();
 			return;
 		}

src/mainboard/google/octopus/variants/baseboard/memory.c

@@ -210,7 +210,7 @@ const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
 
 	if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
 		/* Fall back non cbi memory config. */
-		if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN)
+		if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN)
 			return &non_cbi_lp4cfg;
 	}
 

src/mainboard/google/smaug/pmic.c

@@ -36,10 +36,6 @@ struct max77620_init_reg {
 	u8 delay;
 };
 
-static struct max77620_init_reg init_list[] = {
-	/* TODO */
-};
-
 static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val,
 			   int delay)
 {
@@ -66,20 +62,8 @@ static inline void pmic_write_reg_77621(unsigned bus, uint8_t reg, uint8_t val,
 	pmic_write_reg(bus, MAX77621_CPU_I2C_ADDR, reg, val, delay);
 }
 
-static void pmic_slam_defaults(unsigned bus)
-{
-	int i;
-	for (i = 0; i < ARRAY_SIZE(init_list); i++) {
-		struct max77620_init_reg *reg = &init_list[i];
-		pmic_write_reg_77620(bus, reg->reg, reg->val, reg->delay);
-	}
-}
-
 void pmic_init(unsigned bus)
 {
-	/* Restore PMIC POR defaults, in case kernel changed 'em */
-	pmic_slam_defaults(bus);
-
 	/* MAX77620: Set SD0 to 1.0V - VDD_CORE */
 	pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1);
 	pmic_write_reg_77620(bus, MAX77620_VDVSSD0_REG, 0x20, 1);

src/soc/intel/broadwell/lpc.c

@@ -502,7 +502,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
 #define LPC_DEFAULT_IO_RANGE_LOWER 0
 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
 
-static inline int pch_io_range_in_default(u16 base, u16 size)
+static inline int pch_io_range_in_default(int base, int size)
 {
 	/* Does it start above the range? */
 	if (base >= LPC_DEFAULT_IO_RANGE_UPPER)

src/soc/qualcomm/ipq40xx/qup.c

@@ -478,8 +478,7 @@ qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state)
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 	unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE));
 
-	if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE)
-		&& (curr_state & QUP_STATE_VALID_MASK)) {
+	if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) {
 		/*
 		* For PAUSE_STATE to RESET_STATE transition,
 		* two writes of  10[binary]) are required for the

src/soc/qualcomm/ipq40xx/spi.c

@@ -648,8 +648,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
 {
 	struct ipq_spi_slave *ds = NULL;
 	int i;
-	unsigned int bus = slave->bus;
-	unsigned int cs = slave->cs;
+	int bus = slave->bus;
+	int cs = slave->cs;
 
 	if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI)
 		|| ((bus == BLSP0_SPI) && (cs > 2))

src/soc/qualcomm/ipq806x/qup.c

@@ -379,8 +379,7 @@ qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state)
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 	unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE));
 
-	if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE)
-		&& (curr_state & QUP_STATE_VALID_MASK)) {
+	if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) {
 		/*
 		* For PAUSE_STATE to RESET_STATE transition,
 		* two writes of  10[binary]) are required for the

src/soc/qualcomm/ipq806x/spi.c

@@ -760,8 +760,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
 {
 	struct ipq_spi_slave *ds = NULL;
 	int i;
-	unsigned int bus = slave->bus;
-	unsigned int cs = slave->cs;
+	int bus = slave->bus;
+	int cs = slave->cs;
 
 	/*
 	 * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash

src/soc/rockchip/common/spi.c

@@ -96,7 +96,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
 
 void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
 {
-	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+	assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
 	struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
 	unsigned int ctrlr0 = 0;
 
@@ -134,13 +134,13 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
 
 void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns)
 {
-	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+	assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
 	struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
 	unsigned int rsd;
 
 	/* Rxd Sample Delay */
 	rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8);
-	assert(rsd >= 0 && rsd <= 3);
+	assert(rsd <= 3);
 	clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET,
 			rsd << SPI_RXDSD_OFFSET);
 }

src/soc/samsung/exynos5420/spi.c

@@ -206,7 +206,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 
 static int spi_ctrlr_setup(const struct spi_slave *slave)
 {
-	ASSERT(slave->bus >= 0 && slave->bus < 3);
+	ASSERT(slave->bus < 3);
 	struct exynos_spi_slave *eslave;
 
 	eslave = to_exynos_spi(slave);

src/southbridge/intel/lynxpoint/lpc.c

@@ -623,7 +623,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
 #define LPC_DEFAULT_IO_RANGE_LOWER 0
 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
 
-static inline int pch_io_range_in_default(u16 base, u16 size)
+static inline int pch_io_range_in_default(int base, int size)
 {
 	/* Does it start above the range? */
 	if (base >= LPC_DEFAULT_IO_RANGE_UPPER)

src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c

@@ -527,7 +527,6 @@ NbSmuReadEfuseField (
   UINT32  Address;
   UINT16  Shift;
   ASSERT (Length <= 32);
-  ASSERT (Chain <= 0xff);
   Shift = (Offset - (Offset & ~0x7));
   Address = 0xFE000000 | (Chain << 12) | (Offset >> 3);
   Value = NbSmuReadEfuse (Address, StdHeader);

src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c

@@ -506,7 +506,6 @@ NbSmuReadEfuseField (
   UINT32  Address;
   UINT16  Shift;
   ASSERT (Length <= 32);
-  ASSERT (Chain <= 0xff);
   Shift = (Offset - (Offset & ~0x7));
   Address = 0xFE000000 | (Chain << 12) | (Offset >> 3);
   Value = NbSmuReadEfuse (Address, StdHeader);

src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c

@@ -331,7 +331,7 @@ DmiF15TnGetVoltage (
   LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
   MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
 
-  if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) {
+  if ((MaxVid >= 0xF8)) {
     Voltage = 0;
   } else {
     Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000);

src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c

@@ -62,6 +62,9 @@
 CODE_GROUP (G3_DXE)
 RDATA_GROUP (G3_DXE)
 
+/* Don't warn when checking header-defined ranges that may start at 0. */
+#pragma GCC diagnostic ignored "-Wtype-limits"
+
 #define FILECODE PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE
 
 /**

src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c

@@ -287,7 +287,7 @@ DmiF16KbGetVoltage (
   LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
   MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
 
-  if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) {
+  if ((MaxVid >= 0xF8)) {
     Voltage = 0;
   } else {
     Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000);

src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c

@@ -63,6 +63,9 @@
 CODE_GROUP (G3_DXE)
 RDATA_GROUP (G3_DXE)
 
+/* Don't warn when checking header-defined ranges that may start at 0. */
+#pragma GCC diagnostic ignored "-Wtype-limits"
+
 #define FILECODE PROC_IDS_FAMILY_0X16_KB_IDSF16KBALLSERVICE_FILECODE
 
 /**

src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c

@@ -136,7 +136,7 @@ MemPGetMaxFreqSupported (
   UINT16 MaxFreqSupported;
   UINT16 *SpeedArray;
   UINT8 DDR3Voltage;
-  UINT8 CurrentVoltage;
+  INT8 CurrentVoltage;
   DIMM_TYPE DimmType;
   CPU_LOGICAL_ID LogicalCpuid;
   UINT8 PackageType;