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fix quartet and S4880 spd initialization. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2003-12-02 17:56:31 +00:00
parent 0f4f1d48d9
commit 7c8d35273f
2 changed files with 25 additions and 12 deletions
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18
src/mainboard/amd/quartet/auto.c
View File

@ -104,7 +104,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
#if ( FAKE_SPDROM != 1 )
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x30
#define SMBUS_HUB 0x18
unsigned device=(ctrl->channel0[0])>>8;
smbus_write_byte(SMBUS_HUB , 0x01, device);
smbus_write_byte(SMBUS_HUB , 0x03, 0);
@ -187,15 +187,15 @@ static void pc87360_enable_serial(void)
pnp_set_iobase0(SIO_BASE, 0x3f8);
}
#define RC0 ((1<<0)<<8)
#define RC1 ((1<<1)<<8)
#define RC2 ((1<<2)<<8)
#define RC3 ((1<<3)<<8)
#define RC0 ((1<<1)<<8)
#define RC1 ((1<<2)<<8)
#define RC2 ((1<<3)<<8)
#define RC3 ((1<<4)<<8)
#define DIMM0 0xa0
#define DIMM1 0xa2
#define DIMM2 0xa4
#define DIMM3 0xa8
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
static void main(void)
{

19
src/southbridge/amd/amd8111/amd8111_early_smbus.c
View File

@ -115,11 +115,10 @@ static int smbus_read_byte(unsigned device, unsigned address)
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
#if 1
if (smbus_wait_until_ready() < 0) {
return;
}
#if 0
/* setup transaction */
/* disable interrupts */
outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
@ -138,9 +137,23 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
/* start the command */
outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
#else
/* by LYH */
outb(0x37,SMBUS_IO_BASE + SMBGSTATUS);
/* set the device I'm talking too */
outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
/* data to send */
outb(val, SMBUS_IO_BASE + SMBHSTDAT);
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* start the command */
outb(0xa, SMBUS_IO_BASE + SMBGCTL);
#endif
/* poll for transaction completion */
smbus_wait_until_done();
#endif
return;
}