src/cpu: Remove unnecessary whitespace before "\n"
Change-Id: Iebdcc659bf2a3e738702c85ee86dbb71b504721a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16279 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -122,7 +122,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
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if((apicid_base+ioapic_num-1)>0xf) {
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// We need to enable APIC EXT ID
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printk(BIOS_INFO, "if the IOAPIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for IOAPIC\n");
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printk(BIOS_INFO, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for IOAPIC\n");
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enable_apic_ext_id(nodes);
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}
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@ -134,7 +134,7 @@ static void enable_fid_change(u8 fid)
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dword |= (u32) fid & 0x1F;
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dword |= 1 << 5; // enable
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pci_write_config32(dev, 0xd4, dword);
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printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
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printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x\n", i,
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dword);
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}
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}
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@ -758,7 +758,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
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* PstatMaxVal is going to be 0 on cold reset anyway ?
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*/
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if (!(pci_read_config32(dev, 0xdc) & (~PS_MAX_VAL_MASK))) {
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printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n");
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printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1\n");
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};
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msr.lo &= ~0xFE000000; // clear nbvid
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@ -355,5 +355,5 @@ void cpubug(void)
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bug784();
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bug118253();
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disablememoryreadorder();
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printk(BIOS_DEBUG, "Done cpubug fixes \n");
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printk(BIOS_DEBUG, "Done cpubug fixes\n");
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}
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@ -80,5 +80,5 @@ void cpubug(void)
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{
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pcideadlock();
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disablememoryreadorder();
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printk(BIOS_DEBUG, "Done cpubug fixes \n");
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printk(BIOS_DEBUG, "Done cpubug fixes\n");
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}
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@ -110,7 +110,7 @@ u32 get_apicid_base(u32 ioapic_num)
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if((apicid_base+ioapic_num-1)>0xf) {
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// We need to enable APIC EXT ID
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printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
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printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
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enable_apic_ext_id(sysconf.nodes);
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}
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@ -65,7 +65,7 @@ static inline u32 read_microcode_rev(void)
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"movl $0x01, %%eax\n\t"
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"cpuid\n\t"
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"movl $0x08b, %%ecx\n\t"
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"rdmsr \n\t"
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"rdmsr\n\t"
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: /* outputs */
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"=a" (msr.lo), "=d" (msr.hi)
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: /* inputs */
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@ -145,7 +145,7 @@ static void nano_init(struct device *dev)
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/* We didn't test this on the Nano 1000/2000 series, so warn the user */
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if(c.x86_mask < MODEL_NANO_3000_B0) {
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printk(BIOS_EMERG, "WARNING: This CPU has not been tested. "
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"Please report any issues encountered. \n");
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"Please report any issues encountered.\n");
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}
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switch (c.x86_mask) {
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case MODEL_NANO:
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